read getting closer to being done
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1f9bd2f015
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4 changed files with 78 additions and 52 deletions
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@ -5,12 +5,14 @@
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module Peripherals.Ram(
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initRamFromFile,
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RamAddr,
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Ram,
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RamLine,
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-- Peripherals.Ram.read,
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bytesInRam,
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read,
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write) where
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import Clash.Prelude
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import Clash.Prelude hiding (read)
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import qualified Prelude as P
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import qualified Data.ByteString.Lazy as BL
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import Data.Binary.Get
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@ -18,6 +20,15 @@ import Data.Int (Int32)
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import qualified Clash.Sized.Vector as Vec
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import Types(Addr,
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Byte, HalfWord, FullWord, DoubleWord, QuadWord)
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import BusTypes(
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BusError(..),
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TransactionSize(..),
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Request(..),
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BusResponse(..),
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BusVal(..),
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ReadResponse(..),
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WriteResponse(..)
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)
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-- vector depth has to be known statically at compile time
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#ifndef _RAM_DEPTH
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@ -28,46 +39,54 @@ import Types(Addr,
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type Ram = Vec _RAM_DEPTH (Unsigned 32)
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type RamAddr = Unsigned (CLog 2 _RAM_DEPTH)
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type RamLine = Unsigned 32
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bytesInRam = 1024 * 4
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bytesInRam :: Addr
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bytesInRam = _RAM_DEPTH * 4
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readByte0 :: Ram -> RamAddr -> Byte
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readByte0 ram addr = unpack $ slice d31 d24 word
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where word = ram !! addr
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readByte1 :: Ram -> RamAddr -> Byte
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readByte1 ram addr = unpack $ slice d23 d16 word
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where word = ram !! addr
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readByte2 :: Ram -> RamAddr -> Byte
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readByte2 ram addr = unpack $ slice d15 d8 word
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where word = ram !! addr
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readByte3 :: Ram -> RamAddr -> Byte
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readByte3 ram addr = unpack $ slice d7 d0 word
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where word = ram !! addr
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readHalfWord0 :: Ram -> RamAddr -> HalfWord
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readHalfWord0 ram addr = unpack $ slice d31 d16 word
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where word = ram !! addr
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readHalfWord1 :: Ram -> RamAddr -> HalfWord
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readHalfWord1 ram addr = unpack $ slice d15 d0 word
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where word = ram !! addr
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readFullWord :: Ram -> RamAddr -> FullWord
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readFullWord ram addr = ram !! addr
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readDoubleWord :: Ram -> RamAddr -> DoubleWord
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readDoubleWord ram addr = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
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read :: TransactionSize -> RamAddr -> Ram -> BusVal
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read SizeByte addr ram = BusByte $ unpack byte
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where
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word0 = readFullWord ram addr
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word1 = readFullWord ram (addr + 1)
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word = ram !! addr
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byteOffset :: BitVector 2
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byteOffset = slice d1 d0 addr
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byte = case byteOffset of
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0b00 -> slice d31 d24 word
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0b01 -> slice d23 d16 word
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0b10 -> slice d15 d8 word
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0b11 -> slice d7 d0 word
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readQuadWord :: Ram -> RamAddr -> QuadWord
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readQuadWord ram addr = bitCoerce $ bitCoerce dword0 ++# bitCoerce dword1
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read SizeHalfWord addr ram = BusHalfWord $ unpack halfWord
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where
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dword0 = readDoubleWord ram addr
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dword1 = readDoubleWord ram (addr + 2)
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word = ram !! addr
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halfWordOffset :: Unsigned 1
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halfWordOffset = unpack $ slice d0 d0 addr
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halfWord = case halfWordOffset of
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0b0 -> slice d31 d16 word
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0b1 -> slice d15 d0 word
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read SizeFullWord addr ram = BusFullWord fullWord
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where
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fullWord = ram !! addr
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read SizeDoubleWord addr ram = BusDoubleWord doubleWord
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where
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doubleWord = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
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word0 = readFullWordHelper ram addr
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word1 = readFullWordHelper ram (addr + 1)
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read SizeQuadWord addr ram = BusQuadWord quadWord
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where
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quadWord = bitCoerce $ bitCoerce dword0 ++# bitCoerce dword1
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dword0 = readDoubleWordHelper ram addr
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dword1 = readDoubleWordHelper ram (addr + 2)
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readFullWordHelper :: Ram -> RamAddr -> FullWord
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readFullWordHelper ram addr = ram !! addr
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readDoubleWordHelper :: Ram -> RamAddr -> DoubleWord
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readDoubleWordHelper ram addr = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
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where
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word0 = readFullWordHelper ram addr
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word1 = readFullWordHelper ram (addr + 1)
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write :: Ram -> RamAddr -> RamLine -> Ram
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write ram addr value = replace addr value ram
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