working on adding read stage

hs/Decode.hs

@@ -158,15 +158,6 @@ decodeUType insn = case opcode of
     rd     = getRd     insn
     imm20  = getImm20UType insn
 
-getImm21JType :: Insn -> Unsigned 21
-getImm21JType instr = bitCoerce |> imm20 ++# imm10_1 ++# imm11 ++# imm19_12 ++# zero
-  where
-    imm20    = slice d31 d31 (pack instr)      -- imm[20]
-    imm10_1  = slice d30 d21 (pack instr)      -- imm[10:1]
-    imm11    = slice d20 d20 (pack instr)      -- imm[11]
-    imm19_12 = slice d19 d12 (pack instr)      -- imm[19:12]
-    zero     = 0 :: BitVector 1                -- LSB always zero for J-type
-
 decodeJType :: Insn -> Maybe Opcode
 decodeJType insn =
   case opcode of
@@ -177,6 +168,15 @@ decodeJType insn =
     rd     = getRd insn
     imm21  = getImm21JType insn
 
+getImm21JType :: Insn -> Unsigned 21
+getImm21JType instr = bitCoerce |> imm20 ++# imm10_1 ++# imm11 ++# imm19_12 ++# zero
+  where
+    imm20    = slice d31 d31 (pack instr)      -- imm[20]
+    imm10_1  = slice d30 d21 (pack instr)      -- imm[10:1]
+    imm11    = slice d20 d20 (pack instr)      -- imm[11]
+    imm19_12 = slice d19 d12 (pack instr)      -- imm[19:12]
+    zero     = 0 :: BitVector 1                -- LSB always zero for J-type
+
 getOpcode :: Insn -> Unsigned 7
 getOpcode instr = bitCoerce |> slice d6 d0 (pack instr)
 

hs/Execute.hs

@@ -0,0 +1,6 @@
+{-# LANGUAGE DataKinds #-}
+{-# LANGUAGE NumericUnderscores #-}
+
+module Execute(execute) where
+
+execute = 1

hs/Read.hs

@@ -0,0 +1,6 @@
+{-# LANGUAGE DataKinds #-}
+{-# LANGUAGE NumericUnderscores #-}
+
+module Read(read) where
+
+read = 2

rv_formal.cabal

@@ -87,8 +87,11 @@ library
   exposed-modules:
     Simulation
   other-modules:
+    Fetch,
     Decode,
     DecodeTypes,
+    Execute,
+    Read,
     Peripherals.Ram,
     Peripherals.Uart,
     Peripherals.UartCFFI,
@@ -99,7 +102,6 @@ library
     BusTypes,
     Cpu,
     RegFiles,
-    Fetch,
     Exceptions,
     Util
   c-sources: c/uart_sim_device.c