added needed context and getting ready to implement execute
This commit is contained in:
Yehowshua Immanuel
parent
b95b2b962a
commit
69f5cdee6a
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@ -15,6 +15,7 @@ import Peripherals.Uart(UartAddr, read, write)
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import BusTypes(
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BusError(..),
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TransactionSize(..),
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WriteRequest(..),
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ReadRequest(..),
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BusVal(..),
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)
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@ -53,7 +54,7 @@ alignCheck addr SizeQuadWord = addr `mod` 16 == 0
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-- reading/writing from/to UART is implemented as reading/writing
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-- from/to stdin/stdout, so we need IO.
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read :: ReadRequest -> Peripherals -> IO ReadResponse
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read (Request addr size) peripherals
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read (ReadRequest addr size) peripherals
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| not (alignCheck addr size) = return |> Left UnAligned
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| (addr >= ramStart) && (addr <= ramEnd) =
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return |> Right |> Peripherals.Ram.read size ramWordAddr (ram peripherals)
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@ -71,8 +72,8 @@ read (Request addr size) peripherals
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uartAddr :: UartAddr
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uartAddr = resize uartAddrNoOffset
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write :: BusVal -> Addr -> Peripherals -> IO WriteResponse
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write val addr peripherals
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write :: WriteRequest -> Peripherals -> IO WriteResponse
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write (WriteRequest addr val) peripherals
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| not (alignCheck addr |> busValToTransactionSize val) = return |> Left UnAligned
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| (addr >= uartStart) && (addr <= uartEnd) =
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do
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@ -3,6 +3,7 @@ module BusTypes(
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BusError(..),
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TransactionSize(..),
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ReadRequest(..),
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WriteRequest(..),
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BusVal(..),
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) where
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@ -23,9 +24,14 @@ data TransactionSize
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| SizeQuadWord
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deriving (Generic, Show, Eq, NFDataX)
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data ReadRequest = Request Addr TransactionSize
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data ReadRequest = ReadRequest Addr TransactionSize
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deriving (Generic, Show, Eq, NFDataX)
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data WriteRequest = WriteRequest Addr BusVal
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deriving (Generic, Show, Eq, NFDataX)
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-- data WriteRequest
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data BusVal
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= BusByte Byte
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| BusHalfWord HalfWord
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18
hs/Decode.hs
18
hs/Decode.hs
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@ -11,22 +11,22 @@ import DecodeTypes(
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import Clash.Prelude
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import Fetch(FetchResult (Instruction, InstructionException))
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import Exceptions(Exception(..))
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import Types(Insn)
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import Types(Insn, Addr)
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import RegFiles(RegVal(..))
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import Util((|>))
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data DecodeResult = Opcode Opcode
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| DecodeException Exception
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| InstructionException Exception
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data DecodeResult = Opcode {opcode :: Opcode, insnAddr :: Addr}
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| DecodeException {exception :: Exception, insnAddr :: Addr}
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| InstructionException {exception :: Exception, insnAddr :: Addr}
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deriving (Generic, Show, Eq, NFDataX)
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decode :: FetchResult -> DecodeResult
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decode (Instruction insn) =
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decode (Instruction insn addr) =
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case insnToOpcode insn of
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Just opcode -> Opcode opcode
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Nothing -> DecodeException |> IllegalInstruction insn
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decode (Fetch.InstructionException exception) =
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Decode.InstructionException exception
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Just opcode -> Opcode opcode addr
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Nothing -> DecodeException (IllegalInstruction insn) addr
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decode (Fetch.InstructionException exception addr) =
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Decode.InstructionException exception addr
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insnToOpcode :: Insn -> Maybe Opcode
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insnToOpcode insn =
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@ -18,9 +18,9 @@ data Exception =
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| SupervisorExternalInterrupt
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| MachineExternalInterrupt
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| CounterOverflowInterrupt
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| InstructionAddressMisaligned Addr
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| InstructionAccessFault Addr
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| IllegalInstruction Insn
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| InstructionAddressMisaligned
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| InstructionAccessFault
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| IllegalInstruction {insn :: Insn}
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| Breakpoint
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| LoadAddressMisaligned
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| LoadAccessFault
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@ -45,8 +45,8 @@ exceptionCode MachineTimerInterrupt = 7
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exceptionCode SupervisorExternalInterrupt = 9
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exceptionCode MachineExternalInterrupt = 11
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exceptionCode CounterOverflowInterrupt = 13
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exceptionCode (InstructionAddressMisaligned _) = 0
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exceptionCode (InstructionAccessFault _) = 1
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exceptionCode InstructionAddressMisaligned = 0
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exceptionCode InstructionAccessFault = 1
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exceptionCode (IllegalInstruction _) = 2
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exceptionCode Breakpoint = 3
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exceptionCode LoadAddressMisaligned = 4
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@ -71,8 +71,8 @@ isSynchronousException MachineTimerInterrupt = False
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isSynchronousException SupervisorExternalInterrupt = False
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isSynchronousException MachineExternalInterrupt = False
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isSynchronousException CounterOverflowInterrupt = False
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isSynchronousException (InstructionAddressMisaligned _) = True
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isSynchronousException (InstructionAccessFault _) = True
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isSynchronousException InstructionAddressMisaligned = True
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isSynchronousException InstructionAccessFault = True
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isSynchronousException (IllegalInstruction _) = True
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isSynchronousException Breakpoint = True
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isSynchronousException LoadAddressMisaligned = True
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@ -3,4 +3,21 @@
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module Execute(execute) where
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execute = 1
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import Clash.Prelude
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import Decode(DecodeResult(..))
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import DecodeTypes(Opcode(..))
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import Types(Addr, DoubleWord)
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import BusTypes(
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WriteRequest(..),
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ReadRequest(..),
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)
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import RegFiles(RegFileIdx)
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import Util((|>))
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data ExecuteResult = ReadRequest {readRequest :: ReadRequest, insnAddr :: Addr}
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| WriteRequest {writeRequest :: WriteRequest, insnAddr :: Addr}
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| WriteBackGPR {idx :: RegFileIdx, val :: DoubleWord}
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execute :: DecodeResult -> ExecuteResult
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execute = undefined
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32
hs/Fetch.hs
32
hs/Fetch.hs
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@ -20,32 +20,32 @@ import BusTypes(
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import Exceptions(Exception(..))
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import Util((|>))
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data FetchResult = Instruction Insn
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| InstructionException Exception
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data FetchResult = Instruction {insn :: Insn, insnAddr :: Addr}
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| InstructionException {exception :: Exception, addr :: Addr}
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deriving (Generic, Show, Eq, NFDataX)
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fetchInstruction :: Peripherals -> Addr -> IO FetchResult
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fetchInstruction peripherals addr =
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do
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readReasponse <-Bus.read (BusTypes.Request addr BusTypes.SizeFullWord) peripherals
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readReasponse <-Bus.read (BusTypes.ReadRequest addr BusTypes.SizeFullWord) peripherals
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case readReasponse of
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Right (BusFullWord insn) ->
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pure |> Instruction insn
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pure |> Instruction insn addr
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Left UnAligned ->
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pure |> InstructionException (InstructionAddressMisaligned addr)
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pure |> InstructionException InstructionAddressMisaligned addr
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Left UnMapped ->
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pure |> InstructionException (InstructionAccessFault addr)
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pure |> InstructionException InstructionAccessFault addr
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Right _ ->
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pure |> InstructionException (InstructionAccessFault addr)
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pure |> InstructionException InstructionAccessFault addr
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debugInsn :: FetchResult -> String
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debugInsn fetchResult =
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case fetchResult of
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Instruction insn ->
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"Instruction raw binary | "
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P.++ binaryInsn
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P.++ " (" P.++ show insn P.++ ")"
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where
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binaryInsn = show (bitCoerce insn :: BitVector 32)
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InstructionException e -> show e
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debugInsn = show
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-- case fetchResult of
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-- Instruction insn ->
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-- "Instruction raw binary | "
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-- P.++ binaryInsn
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-- P.++ " (" P.++ show insn P.++ ")"
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-- where
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-- binaryInsn = show (bitCoerce insn :: BitVector 32)
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-- InstructionException e -> show e
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92
hs/Read.hs
92
hs/Read.hs
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@ -15,61 +15,65 @@ import Cpu(RISCVCPU(..))
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import RegFiles (RegVal(..), GPR)
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read :: DecodeResult -> RISCVCPU -> DecodeResult
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read (Opcode opc) riscvCPU =
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let gprRegFile = gpr riscvCPU
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in case opc of
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read (Opcode opcode addr) riscvCPU =
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let
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gprRegFile = gpr riscvCPU
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opcode' = case opcode of
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-- R-Type
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ADD fields -> Opcode (ADD (readRTypeFields fields gprRegFile))
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SUB fields -> Opcode (SUB (readRTypeFields fields gprRegFile))
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XOR fields -> Opcode (XOR (readRTypeFields fields gprRegFile))
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OR fields -> Opcode (OR (readRTypeFields fields gprRegFile))
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AND fields -> Opcode (AND (readRTypeFields fields gprRegFile))
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SLL fields -> Opcode (SLL (readRTypeFields fields gprRegFile))
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SRL fields -> Opcode (SRL (readRTypeFields fields gprRegFile))
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SRA fields -> Opcode (SRA (readRTypeFields fields gprRegFile))
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SLT fields -> Opcode (SLT (readRTypeFields fields gprRegFile))
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SLTU fields -> Opcode (SLTU (readRTypeFields fields gprRegFile))
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ADD fields -> (ADD (readRTypeFields fields gprRegFile))
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SUB fields -> (SUB (readRTypeFields fields gprRegFile))
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XOR fields -> (XOR (readRTypeFields fields gprRegFile))
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OR fields -> (OR (readRTypeFields fields gprRegFile))
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AND fields -> (AND (readRTypeFields fields gprRegFile))
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SLL fields -> (SLL (readRTypeFields fields gprRegFile))
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SRL fields -> (SRL (readRTypeFields fields gprRegFile))
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SRA fields -> (SRA (readRTypeFields fields gprRegFile))
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SLT fields -> (SLT (readRTypeFields fields gprRegFile))
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SLTU fields -> (SLTU (readRTypeFields fields gprRegFile))
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-- I-Type
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ADDI fields -> Opcode (ADDI (readITypeFields fields gprRegFile))
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XORI fields -> Opcode (XORI (readITypeFields fields gprRegFile))
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ORI fields -> Opcode (ORI (readITypeFields fields gprRegFile))
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ANDI fields -> Opcode (ANDI (readITypeFields fields gprRegFile))
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SLLI fields -> Opcode (SLLI (readITypeFields fields gprRegFile))
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SRLI fields -> Opcode (SRLI (readITypeFields fields gprRegFile))
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SRAI fields -> Opcode (SRAI (readITypeFields fields gprRegFile))
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SLTI fields -> Opcode (SLTI (readITypeFields fields gprRegFile))
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SLTIU fields -> Opcode (SLTIU (readITypeFields fields gprRegFile))
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LB fields -> Opcode (LB (readITypeFields fields gprRegFile))
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LH fields -> Opcode (LH (readITypeFields fields gprRegFile))
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LW fields -> Opcode (LW (readITypeFields fields gprRegFile))
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LBU fields -> Opcode (LBU (readITypeFields fields gprRegFile))
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LHU fields -> Opcode (LHU (readITypeFields fields gprRegFile))
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JALR fields -> Opcode (JALR (readITypeFields fields gprRegFile))
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ECALL fields -> Opcode (ECALL (readITypeFields fields gprRegFile)) -- No regs needed, but consistent
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EBREAK fields -> Opcode (EBREAK (readITypeFields fields gprRegFile)) -- Ditto
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ADDI fields -> (ADDI (readITypeFields fields gprRegFile))
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XORI fields -> (XORI (readITypeFields fields gprRegFile))
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ORI fields -> (ORI (readITypeFields fields gprRegFile))
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ANDI fields -> (ANDI (readITypeFields fields gprRegFile))
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SLLI fields -> (SLLI (readITypeFields fields gprRegFile))
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SRLI fields -> (SRLI (readITypeFields fields gprRegFile))
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SRAI fields -> (SRAI (readITypeFields fields gprRegFile))
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SLTI fields -> (SLTI (readITypeFields fields gprRegFile))
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SLTIU fields -> (SLTIU (readITypeFields fields gprRegFile))
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LB fields -> (LB (readITypeFields fields gprRegFile))
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LH fields -> (LH (readITypeFields fields gprRegFile))
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LW fields -> (LW (readITypeFields fields gprRegFile))
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LBU fields -> (LBU (readITypeFields fields gprRegFile))
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LHU fields -> (LHU (readITypeFields fields gprRegFile))
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JALR fields -> (JALR (readITypeFields fields gprRegFile))
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ECALL fields -> (ECALL (readITypeFields fields gprRegFile)) -- No regs needed, but consistent
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EBREAK fields -> (EBREAK (readITypeFields fields gprRegFile)) -- Ditto
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-- S-Type
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SB fields -> Opcode (SB (readSTypeFields fields gprRegFile))
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SH fields -> Opcode (SH (readSTypeFields fields gprRegFile))
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SW fields -> Opcode (SW (readSTypeFields fields gprRegFile))
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SB fields -> (SB (readSTypeFields fields gprRegFile))
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SH fields -> (SH (readSTypeFields fields gprRegFile))
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SW fields -> (SW (readSTypeFields fields gprRegFile))
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-- B-Type
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BEQ fields -> Opcode (BEQ (readBTypeFields fields gprRegFile))
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BNE fields -> Opcode (BNE (readBTypeFields fields gprRegFile))
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BLT fields -> Opcode (BLT (readBTypeFields fields gprRegFile))
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BGE fields -> Opcode (BGE (readBTypeFields fields gprRegFile))
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BLTU fields -> Opcode (BLTU (readBTypeFields fields gprRegFile))
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BGEU fields -> Opcode (BGEU (readBTypeFields fields gprRegFile))
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BEQ fields -> (BEQ (readBTypeFields fields gprRegFile))
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BNE fields -> (BNE (readBTypeFields fields gprRegFile))
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BLT fields -> (BLT (readBTypeFields fields gprRegFile))
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BGE fields -> (BGE (readBTypeFields fields gprRegFile))
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BLTU fields -> (BLTU (readBTypeFields fields gprRegFile))
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BGEU fields -> (BGEU (readBTypeFields fields gprRegFile))
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-- U-Type
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LUI fields -> Opcode (LUI (readUTypeFields fields gprRegFile))
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AUIPC fields -> Opcode (AUIPC (readUTypeFields fields gprRegFile))
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LUI fields -> (LUI (readUTypeFields fields gprRegFile))
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AUIPC fields -> (AUIPC (readUTypeFields fields gprRegFile))
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-- J-Type
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JAL fields -> Opcode (JAL (readJTypeFields fields gprRegFile))
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read (DecodeException e) _ = DecodeException e
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read (InstructionException e) _ = InstructionException e
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JAL fields -> (JAL (readJTypeFields fields gprRegFile))
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in
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Opcode opcode' addr
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read (DecodeException e addr) _ = DecodeException e addr
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read (InstructionException e addr) _ = InstructionException e addr
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readRTypeFields :: RTypeFields -> GPR -> RTypeFields
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readRTypeFields (RTypeFields rd funct3 rs1 rs2 funct7) gprRegFile =
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