bus architecture re-built I think

hs/Peripherals/Ram.hs

@@ -10,7 +10,8 @@ module Peripherals.Ram(
   RamLine,
   bytesInRam,
   read,
-  write) where
+  write,
+  ) where
 
 import Clash.Prelude hiding (read)
 import qualified Prelude as P
@@ -23,8 +24,6 @@ import Types(Addr,
 import BusTypes(
     TransactionSize(..),
     BusVal(..),
-    ReadResponse(..),
-    WriteResponse(..)
   )
 
 -- vector depth has to be known statically at compile time
@@ -85,9 +84,50 @@ readDoubleWordHelper ram addr = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
     word0 = readFullWordHelper ram addr
     word1 = readFullWordHelper ram (addr + 1)
 
--- write :: BusVal -> UartAddr -> IO ()
-write :: Ram -> RamAddr -> RamLine -> Ram
-write ram addr value = replace addr value ram
+write :: BusVal -> RamAddr -> Ram -> Ram
+write (BusByte byte) addr ram = replace addr updatedWord ram
+  where
+    word = ram !! addr
+    byteOffset :: BitVector 2
+    byteOffset = slice d1 d0 addr
+    updatedWord = case byteOffset of
+      0b00 -> setSlice d31 d24 (pack byte) word
+      0b01 -> setSlice d23 d16 (pack byte) word
+      0b10 -> setSlice d15 d8  (pack byte) word
+      0b11 -> setSlice d7 d0   (pack byte) word
+
+write (BusHalfWord halfWord) addr ram = replace addr updatedWord ram
+  where
+    word = ram !! addr
+    halfWordOffset :: Unsigned 1
+    halfWordOffset = unpack $ slice d0 d0 addr
+    updatedWord = case halfWordOffset of
+      0b0 -> setSlice d31 d16 (pack halfWord) word
+      0b1 -> setSlice d15 d0  (pack halfWord) word
+
+write (BusFullWord fullWord) addr ram = replace addr fullWord ram
+
+write (BusDoubleWord doubleWord) addr ram = ram''
+  where
+    (word0, word1) = bitCoerce doubleWord
+    ram' = replace addr word0 ram
+    ram'' = replace (addr + 1) word1 ram'
+
+write (BusQuadWord quadWord) addr ram = ram''''
+  where
+    (dword0 :: DoubleWord, dword1 :: DoubleWord) =
+      bitCoerce quadWord
+
+    (word0 :: FullWord, word1 :: FullWord) =
+      bitCoerce dword0
+
+    (word2 :: FullWord, word3 :: FullWord) =
+      bitCoerce dword1
+
+    ram' = replace addr word0 ram
+    ram'' = replace (addr + 1) word1 ram'
+    ram''' = replace (addr + 2) word2 ram''
+    ram'''' = replace (addr + 3) word3 ram'''
 
 initRamFromFile :: FilePath -> IO (Maybe Ram)
 initRamFromFile filePath =

hs/Peripherals/Uart.hs

@@ -17,8 +17,6 @@ import Peripherals.UartCFFI (
 import BusTypes (
     TransactionSize(..),
     BusVal(..),
-    ReadResponse(..),
-    WriteResponse(..)
   )
 import GHC.Generics (URec(UAddr), Generic (from))