Yehowshua/RiscV-Formal
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refactoring towards types that can handle exceptions between stages

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Yehowshua Immanuel 2025-03-04 23:05:52 -05:00
parent d7d698a28c
commit 4729d79b23
2 changed files with 8 additions and 9 deletions
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11
hs/Cpu.hs
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@ -32,8 +32,9 @@ data RISCVCPU = RISCVCPU
riscvCPUInit :: RISCVCPU riscvCPUInit :: RISCVCPU
riscvCPUInit = riscvCPUInit =
RISCVCPU RISCVCPU
0 { pc = 0 -- 0x8000_0000
gprInit , gpr = gprInit
fprInit , fpr = fprInit
csrInit , csr = csrInit
MachineMode , privilegeLevel = MachineMode
}

6
hs/Simulation.hs
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@ -23,6 +23,7 @@ import Fetch(fetchInstruction, FetchResult (Instruction, Misaligned))
import Isa.Decode(decode) import Isa.Decode(decode)
import Debug.Trace import Debug.Trace
import Types (Insn)
data Args = Args { data Args = Args {
firmware :: FilePath firmware :: FilePath
@ -48,9 +49,6 @@ machine' machine =
machineMem = ram $ machinePeripherals machineMem = ram $ machinePeripherals
machineCPU = cpu machine machineCPU = cpu machine
machinePC = pc machineCPU machinePC = pc machineCPU
addr = 0 :: Integer
mem' = replace addr (3) machineMem
peripherals' = machinePeripherals { ram = mem' }
cpu' = machineCPU { pc = machinePC + 4 } cpu' = machineCPU { pc = machinePC + 4 }
in in
@ -60,7 +58,7 @@ machine' machine =
in trace ("Decoded instruction: " P.++ show opcode in trace ("Decoded instruction: " P.++ show opcode
P.++ " | Binary: " P.++ binaryInsn P.++ " | Binary: " P.++ binaryInsn
P.++ " (" P.++ show insn P.++ ")") $ P.++ " (" P.++ show insn P.++ ")") $
machine { cpu = cpu', peripherals = peripherals' } machine { cpu = cpu' }
where where
opcode = decode insn opcode = decode insn
Misaligned addr -> undefined Misaligned addr -> undefined