Replacing $
operator with more readable |>
operator
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parent
2b1c486c17
commit
0792bf3c7d
12 changed files with 122 additions and 101 deletions
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@ -24,6 +24,7 @@ import BusTypes(
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TransactionSize(..),
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BusVal(..),
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)
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import Util((|>))
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-- vector depth has to be known statically at compile time
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#ifndef _RAM_DEPTH
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@ -38,7 +39,7 @@ bytesInRam :: Addr
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bytesInRam = _RAM_DEPTH * 4
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read :: TransactionSize -> RamAddr -> Ram -> BusVal
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read SizeByte addr ram = BusByte $ unpack byte
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read SizeByte addr ram = BusByte |> unpack byte
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where
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word = ram !! addr
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byteOffset :: BitVector 2
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@ -49,11 +50,11 @@ read SizeByte addr ram = BusByte $ unpack byte
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0b10 -> slice d15 d8 word
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0b11 -> slice d7 d0 word
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read SizeHalfWord addr ram = BusHalfWord $ unpack halfWord
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read SizeHalfWord addr ram = BusHalfWord |> unpack halfWord
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where
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word = ram !! addr
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halfWordOffset :: Unsigned 1
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halfWordOffset = unpack $ slice d0 d0 addr
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halfWordOffset = unpack |> slice d0 d0 addr
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halfWord = case halfWordOffset of
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0b0 -> slice d31 d16 word
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0b1 -> slice d15 d0 word
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@ -64,13 +65,13 @@ read SizeFullWord addr ram = BusFullWord fullWord
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read SizeDoubleWord addr ram = BusDoubleWord doubleWord
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where
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doubleWord = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
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doubleWord = bitCoerce |> bitCoerce word0 ++# bitCoerce word1
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word0 = readFullWordHelper ram addr
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word1 = readFullWordHelper ram (addr + 1)
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read SizeQuadWord addr ram = BusQuadWord quadWord
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where
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quadWord = bitCoerce $ bitCoerce dword0 ++# bitCoerce dword1
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quadWord = bitCoerce |> bitCoerce dword0 ++# bitCoerce dword1
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dword0 = readDoubleWordHelper ram addr
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dword1 = readDoubleWordHelper ram (addr + 2)
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@ -78,7 +79,7 @@ readFullWordHelper :: Ram -> RamAddr -> FullWord
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readFullWordHelper ram addr = ram !! addr
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readDoubleWordHelper :: Ram -> RamAddr -> DoubleWord
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readDoubleWordHelper ram addr = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
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readDoubleWordHelper ram addr = bitCoerce |> bitCoerce word0 ++# bitCoerce word1
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where
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word0 = readFullWordHelper ram addr
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word1 = readFullWordHelper ram (addr + 1)
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@ -99,7 +100,7 @@ write (BusHalfWord halfWord) addr ram = replace addr updatedWord ram
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where
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word = ram !! addr
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halfWordOffset :: Unsigned 1
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halfWordOffset = unpack $ slice d0 d0 addr
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halfWordOffset = unpack |> slice d0 d0 addr
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updatedWord = case halfWordOffset of
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0b0 -> setSlice d31 d16 (pack halfWord) word
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0b1 -> setSlice d15 d0 (pack halfWord) word
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@ -136,7 +137,7 @@ initRamFromFile filePath =
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do
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bs <- readFileIntoByteString filePath
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let ints = getInts bs
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pure $ populateVectorFromInt32 ints initRam
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pure |> populateVectorFromInt32 ints initRam
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readFileIntoByteString :: FilePath -> IO BL.ByteString
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readFileIntoByteString filePath = BL.readFile filePath
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@ -163,6 +164,6 @@ populateVectorFromInt32 ::
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populateVectorFromInt32 ls v = Vec.fromList adjustedLs
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where
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vecLen = length v
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adjustedLs = fromIntegral <$> adjustLength vecLen ls
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adjustedLs = fmap fromIntegral (adjustLength vecLen ls)
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adjustLength :: Int -> [Int32] -> [Int32]
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adjustLength n xs = P.take n (xs P.++ P.repeat 0)
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@ -7,6 +7,7 @@ import Peripherals.UartCFFI(initTerminal)
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import Peripherals.Ram (initRamFromFile, Ram)
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import Control.Exception (try)
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import System.IO.Error (ioeGetErrorString)
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import Util((|>))
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type FirmwareFilePath = FilePath
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@ -20,10 +21,10 @@ setupPeripherals firmwareFilePath = do
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initTerminal
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result <- try (initRamFromFile firmwareFilePath)
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return $ case result of
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return |> case result of
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Right (Just ram) -> InitializedPeripherals ram
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Right Nothing -> InitializationError $ firmwareFilePath ++ failure ++ suggestion
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Left e -> InitializationError $ firmwareFilePath ++ failure ++ suggestion ++ " Error: " ++ ioeGetErrorString e
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Right Nothing -> InitializationError |> firmwareFilePath ++ failure ++ suggestion
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Left e -> InitializationError |> firmwareFilePath ++ failure ++ suggestion ++ " Error: " ++ ioeGetErrorString e
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where
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failure = ": Failed to initialize RAM from file!"
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suggestion = " Is the file 4-byte aligned?"
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@ -14,6 +14,7 @@ import BusTypes (
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TransactionSize(..),
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BusVal(..),
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)
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import Util((|>))
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-- based on a 16550 UART which has an address space of 8 bytes
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type UartAddr = Unsigned 3
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@ -47,7 +48,7 @@ buildRBR = do
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-- Reads the Line Status Register (LSR) to check character availability
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buildLSR :: IO Byte
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buildLSR = do
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(char_available :: Byte) <- fromIntegral <$> isCharAvailable
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(char_available :: Byte) <- fmap fromIntegral isCharAvailable
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-- highly unlikely that we overflow stdout buffer, so we set
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-- transmit to always ready
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let (transmit_ready :: Byte) = 0b0010_0000
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@ -56,8 +57,8 @@ buildLSR = do
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-- Updated 'read' function to handle RBR and LSR reads
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read :: TransactionSize -> UartAddr -> IO BusVal
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read size addr
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| addr == rbrAddr = busValFromByte size <$> buildRBR
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| addr == lsrAddr = busValFromByte size <$> buildLSR
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| addr == rbrAddr = fmap (busValFromByte size) buildRBR
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| addr == lsrAddr = fmap (busValFromByte size) buildLSR
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| otherwise = return $ busValFromByte size 0x00
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extractLowestByte :: BusVal -> Byte
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@ -11,6 +11,7 @@ module Peripherals.UartCFFI (
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) where
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import Prelude
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import Util((|>))
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import Foreign.C.Types
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import Data.Char (chr, ord)
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@ -34,7 +35,7 @@ getCharFromTerminal :: IO Char
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getCharFromTerminal = fmap (chr . fromEnum) c_getCharFromTerminal
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writeCharToTerminal :: Char -> IO ()
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writeCharToTerminal char = c_writeCharToTerminal (toEnum $ ord char)
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writeCharToTerminal char = c_writeCharToTerminal (toEnum |> ord char)
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isCharAvailable :: IO Int
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isCharAvailable = fmap fromEnum c_isCharAvailable
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@ -47,4 +48,4 @@ wasCtrlCReceived = fmap fromEnum c_wasCtrlCReceived
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-- Improved version of the ctrlCReceived to use the new wasCtrlCReceived signature
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ctrlCReceived :: IO Bool
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ctrlCReceived = fmap (/= 0) wasCtrlCReceived
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ctrlCReceived = fmap (/= 0) wasCtrlCReceived
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