Uart now has correct write implementation presumably
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8d5cd862ab
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024115e389
6 changed files with 41 additions and 29 deletions
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@ -1,8 +1,8 @@
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module Peripherals.Uart (read) where
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module Peripherals.Uart (read, write, UartAddr) where
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import Clash.Prelude hiding (read)
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import Types (Byte)
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import Data.Char (ord)
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import Data.Char (ord, chr)
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import Peripherals.UartCFFI (
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initTerminal,
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@ -20,6 +20,7 @@ import BusTypes (
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ReadResponse(..),
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WriteResponse(..)
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)
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import GHC.Generics (URec(UAddr), Generic (from))
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-- based on a 16550 UART which has an address space of 8 bytes
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type UartAddr = Unsigned 3
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@ -28,6 +29,9 @@ type UartAddr = Unsigned 3
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rbrAddr :: UartAddr
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rbrAddr = 0x0
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thrAddr :: UartAddr
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thrAddr = 0x0
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-- Line Status Register address
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lsrAddr :: UartAddr
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lsrAddr = 0x5
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@ -50,8 +54,11 @@ buildRBR = do
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-- Reads the Line Status Register (LSR) to check character availability
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buildLSR :: IO Byte
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buildLSR = do
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char_available <- isCharAvailable
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return $ fromIntegral char_available
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(char_available :: Byte) <- fromIntegral <$> isCharAvailable
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-- highly unlikely that we overflow stdout buffer, so we set
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-- transmit to always ready
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let (transmit_ready :: Byte) = 0b0010_0000
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return (char_available .|. transmit_ready)
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-- Updated 'read' function to handle RBR and LSR reads
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read :: TransactionSize -> UartAddr -> IO BusVal
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@ -59,3 +66,18 @@ read size addr
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| addr == rbrAddr = busValFromByte size <$> buildRBR
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| addr == lsrAddr = busValFromByte size <$> buildLSR
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| otherwise = return $ busValFromByte size 0x00
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extractLowestByte :: BusVal -> Byte
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extractLowestByte (BusByte b) = b
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extractLowestByte (BusHalfWord hw) = resize hw
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extractLowestByte (BusFullWord fw) = resize fw
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extractLowestByte (BusDoubleWord dw) = resize dw
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extractLowestByte (BusQuadWord qw) = resize qw
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byteToChar :: Byte -> Char
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byteToChar = chr . fromIntegral
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write :: BusVal -> UartAddr -> IO ()
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write val addr
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| addr == thrAddr = writeCharToTerminal $ byteToChar $ extractLowestByte val
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| otherwise = return ()
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