8261 lines
73 KiB
Plaintext
8261 lines
73 KiB
Plaintext
$comment
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File created using the following command:
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vcd file CPU_Design.msim.vcd -direction
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$end
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$date
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Fri Aug 13 00:18:19 2021
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$end
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$version
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ModelSim Version 10.5b
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$end
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$timescale
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1ps
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$end
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$scope module CPU_Design_vlg_vec_tst $end
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$var reg 1 ! Clock $end
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$var reg 1 " reset $end
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$var wire 1 # ACC_output [15] $end
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$var wire 1 $ ACC_output [14] $end
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$var wire 1 % ACC_output [13] $end
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$var wire 1 & ACC_output [12] $end
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$var wire 1 ' ACC_output [11] $end
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$var wire 1 ( ACC_output [10] $end
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$var wire 1 ) ACC_output [9] $end
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$var wire 1 * ACC_output [8] $end
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$var wire 1 + ACC_output [7] $end
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$var wire 1 , ACC_output [6] $end
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$var wire 1 - ACC_output [5] $end
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$var wire 1 . ACC_output [4] $end
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$var wire 1 / ACC_output [3] $end
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$var wire 1 0 ACC_output [2] $end
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$var wire 1 1 ACC_output [1] $end
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$var wire 1 2 ACC_output [0] $end
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$var wire 1 3 an [3] $end
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$var wire 1 4 an [2] $end
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$var wire 1 5 an [1] $end
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$var wire 1 6 an [0] $end
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$var wire 1 7 rdreq $end
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$var wire 1 8 sseg [6] $end
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$var wire 1 9 sseg [5] $end
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$var wire 1 : sseg [4] $end
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$var wire 1 ; sseg [3] $end
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$var wire 1 < sseg [2] $end
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$var wire 1 = sseg [1] $end
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$var wire 1 > sseg [0] $end
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$var wire 1 ? wrreq $end
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$scope module i1 $end
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$var wire 1 @ gnd $end
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$var wire 1 A vcc $end
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$var wire 1 B unknown $end
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$var tri1 1 C devclrn $end
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$var tri1 1 D devpor $end
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$var tri1 1 E devoe $end
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$var wire 1 F rdreq~output_o $end
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$var wire 1 G wrreq~output_o $end
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$var wire 1 H ACC_output[15]~output_o $end
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$var wire 1 I ACC_output[14]~output_o $end
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$var wire 1 J ACC_output[13]~output_o $end
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$var wire 1 K ACC_output[12]~output_o $end
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$var wire 1 L ACC_output[11]~output_o $end
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$var wire 1 M ACC_output[10]~output_o $end
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$var wire 1 N ACC_output[9]~output_o $end
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$var wire 1 O ACC_output[8]~output_o $end
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$var wire 1 P ACC_output[7]~output_o $end
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$var wire 1 Q ACC_output[6]~output_o $end
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$var wire 1 R ACC_output[5]~output_o $end
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$var wire 1 S ACC_output[4]~output_o $end
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$var wire 1 T ACC_output[3]~output_o $end
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$var wire 1 U ACC_output[2]~output_o $end
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$var wire 1 V ACC_output[1]~output_o $end
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$var wire 1 W ACC_output[0]~output_o $end
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$var wire 1 X an[3]~output_o $end
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$var wire 1 Y an[2]~output_o $end
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$var wire 1 Z an[1]~output_o $end
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$var wire 1 [ an[0]~output_o $end
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$var wire 1 \ sseg[6]~output_o $end
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$var wire 1 ] sseg[5]~output_o $end
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$var wire 1 ^ sseg[4]~output_o $end
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$var wire 1 _ sseg[3]~output_o $end
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$var wire 1 ` sseg[2]~output_o $end
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$var wire 1 a sseg[1]~output_o $end
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$var wire 1 b sseg[0]~output_o $end
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$var wire 1 c Clock~input_o $end
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$var wire 1 d inst6|Add0~0_combout $end
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$var wire 1 e inst6|count~0_combout $end
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$var wire 1 f inst6|Add0~1 $end
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$var wire 1 g inst6|Add0~2_combout $end
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$var wire 1 h inst6|count~1_combout $end
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$var wire 1 i inst6|Add0~3 $end
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$var wire 1 j inst6|Add0~4_combout $end
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$var wire 1 k inst6|Add0~5 $end
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$var wire 1 l inst6|Add0~6_combout $end
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$var wire 1 m inst6|count~2_combout $end
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$var wire 1 n inst6|Equal0~0_combout $end
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$var wire 1 o inst6|Add0~7 $end
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$var wire 1 p inst6|Add0~8_combout $end
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$var wire 1 q inst6|Add0~9 $end
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$var wire 1 r inst6|Add0~10_combout $end
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$var wire 1 s inst6|Add0~11 $end
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$var wire 1 t inst6|Add0~12_combout $end
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$var wire 1 u inst6|Add0~13 $end
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$var wire 1 v inst6|Add0~14_combout $end
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$var wire 1 w inst6|Equal0~1_combout $end
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$var wire 1 x inst6|Add0~15 $end
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$var wire 1 y inst6|Add0~16_combout $end
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$var wire 1 z inst6|Add0~17 $end
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$var wire 1 { inst6|Add0~18_combout $end
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$var wire 1 | inst6|count~3_combout $end
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$var wire 1 } inst6|Add0~19 $end
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$var wire 1 ~ inst6|Add0~20_combout $end
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$var wire 1 !! inst6|count~4_combout $end
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$var wire 1 "! inst6|Add0~21 $end
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$var wire 1 #! inst6|Add0~22_combout $end
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$var wire 1 $! inst6|count~5_combout $end
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$var wire 1 %! inst6|Equal0~2_combout $end
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$var wire 1 &! inst6|Add0~23 $end
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$var wire 1 '! inst6|Add0~24_combout $end
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$var wire 1 (! inst6|count~6_combout $end
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$var wire 1 )! inst6|Add0~25 $end
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$var wire 1 *! inst6|Add0~26_combout $end
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$var wire 1 +! inst6|count~7_combout $end
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$var wire 1 ,! inst6|Add0~27 $end
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$var wire 1 -! inst6|Add0~28_combout $end
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$var wire 1 .! inst6|count~8_combout $end
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$var wire 1 /! inst6|Add0~29 $end
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$var wire 1 0! inst6|Add0~30_combout $end
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$var wire 1 1! inst6|count~9_combout $end
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$var wire 1 2! inst6|Equal0~3_combout $end
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$var wire 1 3! inst6|Equal0~4_combout $end
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$var wire 1 4! inst6|tick~q $end
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$var wire 1 5! inst10|Add0~0_combout $end
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$var wire 1 6! inst10|Add0~1 $end
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$var wire 1 7! inst10|Add0~2_combout $end
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$var wire 1 8! inst10|count~0_combout $end
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$var wire 1 9! inst10|Add0~3 $end
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$var wire 1 :! inst10|Add0~4_combout $end
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$var wire 1 ;! inst10|Add0~5 $end
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$var wire 1 <! inst10|Add0~6_combout $end
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$var wire 1 =! inst10|count~1_combout $end
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$var wire 1 >! inst10|Equal0~0_combout $end
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$var wire 1 ?! inst10|Add0~7 $end
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$var wire 1 @! inst10|Add0~8_combout $end
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$var wire 1 A! inst10|count~2_combout $end
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$var wire 1 B! inst10|Add0~9 $end
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$var wire 1 C! inst10|Add0~10_combout $end
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$var wire 1 D! inst10|count~3_combout $end
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$var wire 1 E! inst10|Add0~11 $end
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$var wire 1 F! inst10|Add0~12_combout $end
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$var wire 1 G! inst10|count~4_combout $end
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$var wire 1 H! inst10|Add0~13 $end
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$var wire 1 I! inst10|Add0~14_combout $end
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$var wire 1 J! inst10|count~5_combout $end
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$var wire 1 K! inst10|Equal0~1_combout $end
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$var wire 1 L! inst10|Add0~15 $end
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$var wire 1 M! inst10|Add0~16_combout $end
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$var wire 1 N! inst10|count~6_combout $end
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$var wire 1 O! inst10|Add0~17 $end
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$var wire 1 P! inst10|Add0~18_combout $end
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$var wire 1 Q! inst10|count~7_combout $end
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$var wire 1 R! inst10|Add0~19 $end
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$var wire 1 S! inst10|Add0~20_combout $end
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$var wire 1 T! inst10|count~8_combout $end
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$var wire 1 U! inst10|Add0~21 $end
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$var wire 1 V! inst10|Add0~22_combout $end
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$var wire 1 W! inst10|count~9_combout $end
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$var wire 1 X! inst10|Equal0~2_combout $end
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$var wire 1 Y! inst10|Add0~23 $end
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$var wire 1 Z! inst10|Add0~24_combout $end
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$var wire 1 [! inst10|count~10_combout $end
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$var wire 1 \! inst10|Add0~25 $end
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$var wire 1 ]! inst10|Add0~26_combout $end
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$var wire 1 ^! inst10|count~11_combout $end
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$var wire 1 _! inst10|Add0~27 $end
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$var wire 1 `! inst10|Add0~28_combout $end
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$var wire 1 a! inst10|count~12_combout $end
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$var wire 1 b! inst10|Add0~29 $end
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$var wire 1 c! inst10|Add0~30_combout $end
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$var wire 1 d! inst10|count~13_combout $end
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$var wire 1 e! inst10|Equal0~3_combout $end
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$var wire 1 f! inst10|Equal0~4_combout $end
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$var wire 1 g! inst10|tick~q $end
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$var wire 1 h! statemachine|FETCH~0_combout $end
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$var wire 1 i! inst|inst~q $end
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$var wire 1 j! ALU|auto_generated|_~2_combout $end
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$var wire 1 k! ALU|auto_generated|result_int[0]~1_cout $end
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$var wire 1 l! ALU|auto_generated|result_int[1]~2_combout $end
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$var wire 1 m! MUX2|$00000|auto_generated|result_node[14]~0_combout $end
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$var wire 1 n! MUX2|$00000|auto_generated|result_node[0]~4_combout $end
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$var wire 1 o! PC|auto_generated|counter_comb_bita0~combout $end
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$var wire 1 p! ALU|auto_generated|_~1_combout $end
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$var wire 1 q! ALU|auto_generated|result_int[14]~29 $end
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$var wire 1 r! ALU|auto_generated|result_int[15]~30_combout $end
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$var wire 1 s! acc|dffs[14]~0_combout $end
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$var wire 1 t! inst7|acc_en~0_combout $end
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$var wire 1 u! MUX2|$00000|auto_generated|result_node[12]~3_combout $end
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$var wire 1 v! inst7|acc_sload~5_combout $end
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$var wire 1 w! inst7|acc_en~combout $end
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$var wire 1 x! inst1|EQ~0_combout $end
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$var wire 1 y! inst1|EQ~1_combout $end
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$var wire 1 z! inst1|EQ~2_combout $end
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$var wire 1 {! inst1|EQ~3_combout $end
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$var wire 1 |! inst1|EQ~4_combout $end
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$var wire 1 }! inst7|cnt_en~0_combout $end
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$var wire 1 ~! inst7|PC_sload~0_combout $end
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$var wire 1 !" inst7|PC_sload~1_combout $end
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$var wire 1 "" inst7|PC_sload~2_combout $end
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$var wire 1 #" inst7|PC_sload~3_combout $end
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$var wire 1 $" inst7|cnt_en~1_combout $end
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$var wire 1 %" inst7|cnt_en~2_combout $end
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$var wire 1 &" PC|auto_generated|_~0_combout $end
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$var wire 1 '" MUX1|$00000|auto_generated|result_node[0]~0_combout $end
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$var wire 1 (" MUX2|$00000|auto_generated|result_node[1]~5_combout $end
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$var wire 1 )" PC|auto_generated|counter_comb_bita0~COUT $end
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$var wire 1 *" PC|auto_generated|counter_comb_bita1~combout $end
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$var wire 1 +" MUX1|$00000|auto_generated|result_node[1]~1_combout $end
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$var wire 1 ," MUX2|$00000|auto_generated|result_node[2]~6_combout $end
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$var wire 1 -" PC|auto_generated|counter_comb_bita1~COUT $end
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$var wire 1 ." PC|auto_generated|counter_comb_bita2~combout $end
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$var wire 1 /" MUX1|$00000|auto_generated|result_node[2]~2_combout $end
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$var wire 1 0" MUX2|$00000|auto_generated|result_node[3]~7_combout $end
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$var wire 1 1" PC|auto_generated|counter_comb_bita2~COUT $end
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$var wire 1 2" PC|auto_generated|counter_comb_bita3~combout $end
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$var wire 1 3" MUX1|$00000|auto_generated|result_node[3]~3_combout $end
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$var wire 1 4" MUX2|$00000|auto_generated|result_node[4]~8_combout $end
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$var wire 1 5" PC|auto_generated|counter_comb_bita3~COUT $end
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$var wire 1 6" PC|auto_generated|counter_comb_bita4~combout $end
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$var wire 1 7" MUX1|$00000|auto_generated|result_node[4]~4_combout $end
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$var wire 1 8" MUX2|$00000|auto_generated|result_node[5]~9_combout $end
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$var wire 1 9" PC|auto_generated|counter_comb_bita4~COUT $end
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$var wire 1 :" PC|auto_generated|counter_comb_bita5~combout $end
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$var wire 1 ;" MUX1|$00000|auto_generated|result_node[5]~5_combout $end
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$var wire 1 <" MUX2|$00000|auto_generated|result_node[6]~10_combout $end
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$var wire 1 =" PC|auto_generated|counter_comb_bita5~COUT $end
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$var wire 1 >" PC|auto_generated|counter_comb_bita6~combout $end
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$var wire 1 ?" MUX1|$00000|auto_generated|result_node[6]~6_combout $end
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$var wire 1 @" MUX2|$00000|auto_generated|result_node[7]~11_combout $end
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$var wire 1 A" PC|auto_generated|counter_comb_bita6~COUT $end
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$var wire 1 B" PC|auto_generated|counter_comb_bita7~combout $end
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$var wire 1 C" MUX1|$00000|auto_generated|result_node[7]~7_combout $end
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$var wire 1 D" MUX2|$00000|auto_generated|result_node[8]~12_combout $end
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$var wire 1 E" PC|auto_generated|counter_comb_bita7~COUT $end
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$var wire 1 F" PC|auto_generated|counter_comb_bita8~combout $end
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$var wire 1 G" MUX1|$00000|auto_generated|result_node[8]~8_combout $end
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$var wire 1 H" MUX2|$00000|auto_generated|result_node[9]~13_combout $end
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$var wire 1 I" PC|auto_generated|counter_comb_bita8~COUT $end
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$var wire 1 J" PC|auto_generated|counter_comb_bita9~combout $end
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$var wire 1 K" MUX1|$00000|auto_generated|result_node[9]~9_combout $end
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$var wire 1 L" MUX2|$00000|auto_generated|result_node[10]~14_combout $end
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$var wire 1 M" PC|auto_generated|counter_comb_bita9~COUT $end
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$var wire 1 N" PC|auto_generated|counter_comb_bita10~combout $end
|
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$var wire 1 O" MUX1|$00000|auto_generated|result_node[10]~10_combout $end
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$var wire 1 P" MUX2|$00000|auto_generated|result_node[11]~15_combout $end
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$var wire 1 Q" PC|auto_generated|counter_comb_bita10~COUT $end
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$var wire 1 R" PC|auto_generated|counter_comb_bita11~combout $end
|
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$var wire 1 S" MUX1|$00000|auto_generated|result_node[11]~11_combout $end
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$var wire 1 T" MUX2|$00000|auto_generated|result_node[15]~1_combout $end
|
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$var wire 1 U" inst7|sel3~1_combout $end
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$var wire 1 V" acc|dffs[0]~14_combout $end
|
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$var wire 1 W" ALU|auto_generated|_~15_combout $end
|
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$var wire 1 X" ALU|auto_generated|result_int[1]~3 $end
|
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$var wire 1 Y" ALU|auto_generated|result_int[2]~4_combout $end
|
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$var wire 1 Z" acc|dffs[1]~13_combout $end
|
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$var wire 1 [" ALU|auto_generated|_~14_combout $end
|
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$var wire 1 \" ALU|auto_generated|result_int[2]~5 $end
|
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$var wire 1 ]" ALU|auto_generated|result_int[3]~6_combout $end
|
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$var wire 1 ^" acc|dffs[2]~12_combout $end
|
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$var wire 1 _" ALU|auto_generated|_~13_combout $end
|
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$var wire 1 `" ALU|auto_generated|result_int[3]~7 $end
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$var wire 1 a" ALU|auto_generated|result_int[4]~8_combout $end
|
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$var wire 1 b" acc|dffs[3]~11_combout $end
|
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$var wire 1 c" ALU|auto_generated|_~12_combout $end
|
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$var wire 1 d" ALU|auto_generated|result_int[4]~9 $end
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$var wire 1 e" ALU|auto_generated|result_int[5]~10_combout $end
|
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$var wire 1 f" acc|dffs[4]~10_combout $end
|
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$var wire 1 g" ALU|auto_generated|_~11_combout $end
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$var wire 1 h" ALU|auto_generated|result_int[5]~11 $end
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$var wire 1 i" ALU|auto_generated|result_int[6]~12_combout $end
|
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$var wire 1 j" acc|dffs[5]~9_combout $end
|
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$var wire 1 k" ALU|auto_generated|_~10_combout $end
|
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$var wire 1 l" ALU|auto_generated|result_int[6]~13 $end
|
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$var wire 1 m" ALU|auto_generated|result_int[7]~14_combout $end
|
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$var wire 1 n" acc|dffs[6]~8_combout $end
|
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$var wire 1 o" ALU|auto_generated|_~9_combout $end
|
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$var wire 1 p" ALU|auto_generated|result_int[7]~15 $end
|
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$var wire 1 q" ALU|auto_generated|result_int[8]~16_combout $end
|
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$var wire 1 r" acc|dffs[7]~7_combout $end
|
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$var wire 1 s" ALU|auto_generated|_~8_combout $end
|
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$var wire 1 t" ALU|auto_generated|result_int[8]~17 $end
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$var wire 1 u" ALU|auto_generated|result_int[9]~18_combout $end
|
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$var wire 1 v" acc|dffs[8]~6_combout $end
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$var wire 1 w" ALU|auto_generated|_~7_combout $end
|
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$var wire 1 x" ALU|auto_generated|result_int[9]~19 $end
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$var wire 1 y" ALU|auto_generated|result_int[10]~20_combout $end
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$var wire 1 z" acc|dffs[9]~5_combout $end
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$var wire 1 {" ALU|auto_generated|_~6_combout $end
|
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$var wire 1 |" ALU|auto_generated|result_int[10]~21 $end
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$var wire 1 }" ALU|auto_generated|result_int[11]~22_combout $end
|
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$var wire 1 ~" acc|dffs[10]~4_combout $end
|
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$var wire 1 !# ALU|auto_generated|_~5_combout $end
|
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$var wire 1 "# ALU|auto_generated|result_int[11]~23 $end
|
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$var wire 1 ## ALU|auto_generated|result_int[12]~24_combout $end
|
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$var wire 1 $# acc|dffs[11]~3_combout $end
|
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$var wire 1 %# ALU|auto_generated|_~4_combout $end
|
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$var wire 1 &# ALU|auto_generated|result_int[12]~25 $end
|
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$var wire 1 '# ALU|auto_generated|result_int[13]~27 $end
|
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$var wire 1 (# ALU|auto_generated|result_int[14]~28_combout $end
|
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$var wire 1 )# acc|dffs[13]~1_combout $end
|
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$var wire 1 *# MUX2|$00000|auto_generated|result_node[13]~2_combout $end
|
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$var wire 1 +# inst7|ADD~0_combout $end
|
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$var wire 1 ,# ALU|auto_generated|_~3_combout $end
|
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$var wire 1 -# ALU|auto_generated|result_int[13]~26_combout $end
|
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$var wire 1 .# acc|dffs[12]~2_combout $end
|
|
$var wire 1 /# inst7|WRen~0_combout $end
|
|
$var wire 1 0# statemachine|NS[1]~0_combout $end
|
|
$var wire 1 1# statemachine|NS[1]~1_combout $end
|
|
$var wire 1 2# inst|inst1~q $end
|
|
$var wire 1 3# inst7|sel3~0_combout $end
|
|
$var wire 1 4# inst7|acc_sload~4_combout $end
|
|
$var wire 1 5# ALU|auto_generated|_~0_combout $end
|
|
$var wire 1 6# ALU|auto_generated|result_int[15]~31 $end
|
|
$var wire 1 7# ALU|auto_generated|result_int[16]~32_combout $end
|
|
$var wire 1 8# ALU|auto_generated|op_1~0_combout $end
|
|
$var wire 1 9# ALU|auto_generated|op_1~1_combout $end
|
|
$var wire 1 :# inst2|regN[0]~51_combout $end
|
|
$var wire 1 ;# reset~input_o $end
|
|
$var wire 1 <# inst2|regN[1]~17_combout $end
|
|
$var wire 1 =# inst2|regN[1]~18 $end
|
|
$var wire 1 ># inst2|regN[2]~19_combout $end
|
|
$var wire 1 ?# inst2|regN[2]~20 $end
|
|
$var wire 1 @# inst2|regN[3]~21_combout $end
|
|
$var wire 1 A# inst2|regN[3]~22 $end
|
|
$var wire 1 B# inst2|regN[4]~23_combout $end
|
|
$var wire 1 C# inst2|regN[4]~24 $end
|
|
$var wire 1 D# inst2|regN[5]~25_combout $end
|
|
$var wire 1 E# inst2|regN[5]~26 $end
|
|
$var wire 1 F# inst2|regN[6]~27_combout $end
|
|
$var wire 1 G# inst2|regN[6]~28 $end
|
|
$var wire 1 H# inst2|regN[7]~29_combout $end
|
|
$var wire 1 I# inst2|regN[7]~30 $end
|
|
$var wire 1 J# inst2|regN[8]~31_combout $end
|
|
$var wire 1 K# inst2|regN[8]~32 $end
|
|
$var wire 1 L# inst2|regN[9]~33_combout $end
|
|
$var wire 1 M# inst2|regN[9]~34 $end
|
|
$var wire 1 N# inst2|regN[10]~35_combout $end
|
|
$var wire 1 O# inst2|regN[10]~36 $end
|
|
$var wire 1 P# inst2|regN[11]~37_combout $end
|
|
$var wire 1 Q# inst2|regN[11]~38 $end
|
|
$var wire 1 R# inst2|regN[12]~39_combout $end
|
|
$var wire 1 S# inst2|regN[12]~40 $end
|
|
$var wire 1 T# inst2|regN[13]~41_combout $end
|
|
$var wire 1 U# inst2|regN[13]~42 $end
|
|
$var wire 1 V# inst2|regN[14]~43_combout $end
|
|
$var wire 1 W# inst2|regN[14]~44 $end
|
|
$var wire 1 X# inst2|regN[15]~45_combout $end
|
|
$var wire 1 Y# inst2|regN[15]~46 $end
|
|
$var wire 1 Z# inst2|regN[16]~47_combout $end
|
|
$var wire 1 [# inst2|regN[16]~48 $end
|
|
$var wire 1 \# inst2|regN[17]~49_combout $end
|
|
$var wire 1 ]# inst2|Decoder0~0_combout $end
|
|
$var wire 1 ^# inst2|Decoder0~1_combout $end
|
|
$var wire 1 _# inst2|Decoder0~2_combout $end
|
|
$var wire 1 `# inst2|Decoder0~3_combout $end
|
|
$var wire 1 a# inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout $end
|
|
$var wire 1 b# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout $end
|
|
$var wire 1 c# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout $end
|
|
$var wire 1 d# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT $end
|
|
$var wire 1 e# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout $end
|
|
$var wire 1 f# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT $end
|
|
$var wire 1 g# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout $end
|
|
$var wire 1 h# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT $end
|
|
$var wire 1 i# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout $end
|
|
$var wire 1 j# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT $end
|
|
$var wire 1 k# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout $end
|
|
$var wire 1 l# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT $end
|
|
$var wire 1 m# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout $end
|
|
$var wire 1 n# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT $end
|
|
$var wire 1 o# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout $end
|
|
$var wire 1 p# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT $end
|
|
$var wire 1 q# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout $end
|
|
$var wire 1 r# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT $end
|
|
$var wire 1 s# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout $end
|
|
$var wire 1 t# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT $end
|
|
$var wire 1 u# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout $end
|
|
$var wire 1 v# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~COUT $end
|
|
$var wire 1 w# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita10~combout $end
|
|
$var wire 1 x# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita10~COUT $end
|
|
$var wire 1 y# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita11~combout $end
|
|
$var wire 1 z# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita11~COUT $end
|
|
$var wire 1 {# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita12~combout $end
|
|
$var wire 1 |# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita12~COUT $end
|
|
$var wire 1 }# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita13~combout $end
|
|
$var wire 1 ~# inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout $end
|
|
$var wire 1 !$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout $end
|
|
$var wire 1 "$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout $end
|
|
$var wire 1 #$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3_combout $end
|
|
$var wire 1 $$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4_combout $end
|
|
$var wire 1 %$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~5_combout $end
|
|
$var wire 1 &$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q $end
|
|
$var wire 1 '$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout $end
|
|
$var wire 1 ($ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout $end
|
|
$var wire 1 )$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout $end
|
|
$var wire 1 *$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout $end
|
|
$var wire 1 +$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout $end
|
|
$var wire 1 ,$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~5_combout $end
|
|
$var wire 1 -$ inst11|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q $end
|
|
$var wire 1 .$ inst11|scfifo_component|auto_generated|dpfifo|valid_wreq~combout $end
|
|
$var wire 1 /$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT $end
|
|
$var wire 1 0$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout $end
|
|
$var wire 1 1$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT $end
|
|
$var wire 1 2$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout $end
|
|
$var wire 1 3$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT $end
|
|
$var wire 1 4$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout $end
|
|
$var wire 1 5$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT $end
|
|
$var wire 1 6$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout $end
|
|
$var wire 1 7$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT $end
|
|
$var wire 1 8$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout $end
|
|
$var wire 1 9$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT $end
|
|
$var wire 1 :$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout $end
|
|
$var wire 1 ;$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT $end
|
|
$var wire 1 <$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout $end
|
|
$var wire 1 =$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT $end
|
|
$var wire 1 >$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout $end
|
|
$var wire 1 ?$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT $end
|
|
$var wire 1 @$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout $end
|
|
$var wire 1 A$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~COUT $end
|
|
$var wire 1 B$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita10~combout $end
|
|
$var wire 1 C$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita10~COUT $end
|
|
$var wire 1 D$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita11~combout $end
|
|
$var wire 1 E$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita11~COUT $end
|
|
$var wire 1 F$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita12~combout $end
|
|
$var wire 1 G$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita12~COUT $end
|
|
$var wire 1 H$ inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita13~combout $end
|
|
$var wire 1 I$ inst11|scfifo_component|auto_generated|dpfifo|valid_rreq~combout $end
|
|
$var wire 1 J$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout $end
|
|
$var wire 1 K$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT $end
|
|
$var wire 1 L$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout $end
|
|
$var wire 1 M$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT $end
|
|
$var wire 1 N$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout $end
|
|
$var wire 1 O$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT $end
|
|
$var wire 1 P$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout $end
|
|
$var wire 1 Q$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT $end
|
|
$var wire 1 R$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout $end
|
|
$var wire 1 S$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT $end
|
|
$var wire 1 T$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout $end
|
|
$var wire 1 U$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT $end
|
|
$var wire 1 V$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout $end
|
|
$var wire 1 W$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT $end
|
|
$var wire 1 X$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout $end
|
|
$var wire 1 Y$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT $end
|
|
$var wire 1 Z$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout $end
|
|
$var wire 1 [$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT $end
|
|
$var wire 1 \$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout $end
|
|
$var wire 1 ]$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~COUT $end
|
|
$var wire 1 ^$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita10~combout $end
|
|
$var wire 1 _$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita10~COUT $end
|
|
$var wire 1 `$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita11~combout $end
|
|
$var wire 1 a$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita11~COUT $end
|
|
$var wire 1 b$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita12~combout $end
|
|
$var wire 1 c$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a24~portbdataout $end
|
|
$var wire 1 d$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita12~COUT $end
|
|
$var wire 1 e$ inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita13~combout $end
|
|
$var wire 1 f$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a12~portbdataout $end
|
|
$var wire 1 g$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a8~portbdataout $end
|
|
$var wire 1 h$ inst2|Mux3~0_combout $end
|
|
$var wire 1 i$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a28~portbdataout $end
|
|
$var wire 1 j$ inst2|Mux3~1_combout $end
|
|
$var wire 1 k$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a16~portbdataout $end
|
|
$var wire 1 l$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a4~portbdataout $end
|
|
$var wire 1 m$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0~portbdataout $end
|
|
$var wire 1 n$ inst2|Mux3~2_combout $end
|
|
$var wire 1 o$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a20~portbdataout $end
|
|
$var wire 1 p$ inst2|Mux3~3_combout $end
|
|
$var wire 1 q$ inst2|Mux3~4_combout $end
|
|
$var wire 1 r$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a25~portbdataout $end
|
|
$var wire 1 s$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a13~portbdataout $end
|
|
$var wire 1 t$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a9~portbdataout $end
|
|
$var wire 1 u$ inst2|Mux2~0_combout $end
|
|
$var wire 1 v$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a29~portbdataout $end
|
|
$var wire 1 w$ inst2|Mux2~1_combout $end
|
|
$var wire 1 x$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a17~portbdataout $end
|
|
$var wire 1 y$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a5~portbdataout $end
|
|
$var wire 1 z$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a1~portbdataout $end
|
|
$var wire 1 {$ inst2|Mux2~2_combout $end
|
|
$var wire 1 |$ inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a21~portbdataout $end
|
|
$var wire 1 }$ inst2|Mux2~3_combout $end
|
|
$var wire 1 ~$ inst2|Mux2~4_combout $end
|
|
$var wire 1 !% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a14~portbdataout $end
|
|
$var wire 1 "% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a26~portbdataout $end
|
|
$var wire 1 #% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a10~portbdataout $end
|
|
$var wire 1 $% inst2|Mux1~0_combout $end
|
|
$var wire 1 %% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a30~portbdataout $end
|
|
$var wire 1 &% inst2|Mux1~1_combout $end
|
|
$var wire 1 '% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a18~portbdataout $end
|
|
$var wire 1 (% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a6~portbdataout $end
|
|
$var wire 1 )% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a2~portbdataout $end
|
|
$var wire 1 *% inst2|Mux1~2_combout $end
|
|
$var wire 1 +% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a22~portbdataout $end
|
|
$var wire 1 ,% inst2|Mux1~3_combout $end
|
|
$var wire 1 -% inst2|Mux1~4_combout $end
|
|
$var wire 1 .% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a15~portbdataout $end
|
|
$var wire 1 /% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a27~portbdataout $end
|
|
$var wire 1 0% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a11~portbdataout $end
|
|
$var wire 1 1% inst2|Mux0~0_combout $end
|
|
$var wire 1 2% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a31~portbdataout $end
|
|
$var wire 1 3% inst2|Mux0~1_combout $end
|
|
$var wire 1 4% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a19~portbdataout $end
|
|
$var wire 1 5% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a7~portbdataout $end
|
|
$var wire 1 6% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a3~portbdataout $end
|
|
$var wire 1 7% inst2|Mux0~2_combout $end
|
|
$var wire 1 8% inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a23~portbdataout $end
|
|
$var wire 1 9% inst2|Mux0~3_combout $end
|
|
$var wire 1 :% inst2|Mux0~4_combout $end
|
|
$var wire 1 ;% inst2|WideOr0~0_combout $end
|
|
$var wire 1 <% inst2|WideOr1~0_combout $end
|
|
$var wire 1 =% inst2|WideOr2~0_combout $end
|
|
$var wire 1 >% inst2|WideOr3~0_combout $end
|
|
$var wire 1 ?% inst2|WideOr4~0_combout $end
|
|
$var wire 1 @% inst2|WideOr5~0_combout $end
|
|
$var wire 1 A% inst2|WideOr6~0_combout $end
|
|
$var wire 1 B% inst10|count [15] $end
|
|
$var wire 1 C% inst10|count [14] $end
|
|
$var wire 1 D% inst10|count [13] $end
|
|
$var wire 1 E% inst10|count [12] $end
|
|
$var wire 1 F% inst10|count [11] $end
|
|
$var wire 1 G% inst10|count [10] $end
|
|
$var wire 1 H% inst10|count [9] $end
|
|
$var wire 1 I% inst10|count [8] $end
|
|
$var wire 1 J% inst10|count [7] $end
|
|
$var wire 1 K% inst10|count [6] $end
|
|
$var wire 1 L% inst10|count [5] $end
|
|
$var wire 1 M% inst10|count [4] $end
|
|
$var wire 1 N% inst10|count [3] $end
|
|
$var wire 1 O% inst10|count [2] $end
|
|
$var wire 1 P% inst10|count [1] $end
|
|
$var wire 1 Q% inst10|count [0] $end
|
|
$var wire 1 R% acc|dffs [15] $end
|
|
$var wire 1 S% acc|dffs [14] $end
|
|
$var wire 1 T% acc|dffs [13] $end
|
|
$var wire 1 U% acc|dffs [12] $end
|
|
$var wire 1 V% acc|dffs [11] $end
|
|
$var wire 1 W% acc|dffs [10] $end
|
|
$var wire 1 X% acc|dffs [9] $end
|
|
$var wire 1 Y% acc|dffs [8] $end
|
|
$var wire 1 Z% acc|dffs [7] $end
|
|
$var wire 1 [% acc|dffs [6] $end
|
|
$var wire 1 \% acc|dffs [5] $end
|
|
$var wire 1 ]% acc|dffs [4] $end
|
|
$var wire 1 ^% acc|dffs [3] $end
|
|
$var wire 1 _% acc|dffs [2] $end
|
|
$var wire 1 `% acc|dffs [1] $end
|
|
$var wire 1 a% acc|dffs [0] $end
|
|
$var wire 1 b% IR1|dffs [15] $end
|
|
$var wire 1 c% IR1|dffs [14] $end
|
|
$var wire 1 d% IR1|dffs [13] $end
|
|
$var wire 1 e% IR1|dffs [12] $end
|
|
$var wire 1 f% IR1|dffs [11] $end
|
|
$var wire 1 g% IR1|dffs [10] $end
|
|
$var wire 1 h% IR1|dffs [9] $end
|
|
$var wire 1 i% IR1|dffs [8] $end
|
|
$var wire 1 j% IR1|dffs [7] $end
|
|
$var wire 1 k% IR1|dffs [6] $end
|
|
$var wire 1 l% IR1|dffs [5] $end
|
|
$var wire 1 m% IR1|dffs [4] $end
|
|
$var wire 1 n% IR1|dffs [3] $end
|
|
$var wire 1 o% IR1|dffs [2] $end
|
|
$var wire 1 p% IR1|dffs [1] $end
|
|
$var wire 1 q% IR1|dffs [0] $end
|
|
$var wire 1 r% inst6|count [15] $end
|
|
$var wire 1 s% inst6|count [14] $end
|
|
$var wire 1 t% inst6|count [13] $end
|
|
$var wire 1 u% inst6|count [12] $end
|
|
$var wire 1 v% inst6|count [11] $end
|
|
$var wire 1 w% inst6|count [10] $end
|
|
$var wire 1 x% inst6|count [9] $end
|
|
$var wire 1 y% inst6|count [8] $end
|
|
$var wire 1 z% inst6|count [7] $end
|
|
$var wire 1 {% inst6|count [6] $end
|
|
$var wire 1 |% inst6|count [5] $end
|
|
$var wire 1 }% inst6|count [4] $end
|
|
$var wire 1 ~% inst6|count [3] $end
|
|
$var wire 1 !& inst6|count [2] $end
|
|
$var wire 1 "& inst6|count [1] $end
|
|
$var wire 1 #& inst6|count [0] $end
|
|
$var wire 1 $& inst2|regN [17] $end
|
|
$var wire 1 %& inst2|regN [16] $end
|
|
$var wire 1 && inst2|regN [15] $end
|
|
$var wire 1 '& inst2|regN [14] $end
|
|
$var wire 1 (& inst2|regN [13] $end
|
|
$var wire 1 )& inst2|regN [12] $end
|
|
$var wire 1 *& inst2|regN [11] $end
|
|
$var wire 1 +& inst2|regN [10] $end
|
|
$var wire 1 ,& inst2|regN [9] $end
|
|
$var wire 1 -& inst2|regN [8] $end
|
|
$var wire 1 .& inst2|regN [7] $end
|
|
$var wire 1 /& inst2|regN [6] $end
|
|
$var wire 1 0& inst2|regN [5] $end
|
|
$var wire 1 1& inst2|regN [4] $end
|
|
$var wire 1 2& inst2|regN [3] $end
|
|
$var wire 1 3& inst2|regN [2] $end
|
|
$var wire 1 4& inst2|regN [1] $end
|
|
$var wire 1 5& inst2|regN [0] $end
|
|
$var wire 1 6& RAM|altsyncram_component|auto_generated|q_a [15] $end
|
|
$var wire 1 7& RAM|altsyncram_component|auto_generated|q_a [14] $end
|
|
$var wire 1 8& RAM|altsyncram_component|auto_generated|q_a [13] $end
|
|
$var wire 1 9& RAM|altsyncram_component|auto_generated|q_a [12] $end
|
|
$var wire 1 :& RAM|altsyncram_component|auto_generated|q_a [11] $end
|
|
$var wire 1 ;& RAM|altsyncram_component|auto_generated|q_a [10] $end
|
|
$var wire 1 <& RAM|altsyncram_component|auto_generated|q_a [9] $end
|
|
$var wire 1 =& RAM|altsyncram_component|auto_generated|q_a [8] $end
|
|
$var wire 1 >& RAM|altsyncram_component|auto_generated|q_a [7] $end
|
|
$var wire 1 ?& RAM|altsyncram_component|auto_generated|q_a [6] $end
|
|
$var wire 1 @& RAM|altsyncram_component|auto_generated|q_a [5] $end
|
|
$var wire 1 A& RAM|altsyncram_component|auto_generated|q_a [4] $end
|
|
$var wire 1 B& RAM|altsyncram_component|auto_generated|q_a [3] $end
|
|
$var wire 1 C& RAM|altsyncram_component|auto_generated|q_a [2] $end
|
|
$var wire 1 D& RAM|altsyncram_component|auto_generated|q_a [1] $end
|
|
$var wire 1 E& RAM|altsyncram_component|auto_generated|q_a [0] $end
|
|
$var wire 1 F& PC|auto_generated|counter_reg_bit [11] $end
|
|
$var wire 1 G& PC|auto_generated|counter_reg_bit [10] $end
|
|
$var wire 1 H& PC|auto_generated|counter_reg_bit [9] $end
|
|
$var wire 1 I& PC|auto_generated|counter_reg_bit [8] $end
|
|
$var wire 1 J& PC|auto_generated|counter_reg_bit [7] $end
|
|
$var wire 1 K& PC|auto_generated|counter_reg_bit [6] $end
|
|
$var wire 1 L& PC|auto_generated|counter_reg_bit [5] $end
|
|
$var wire 1 M& PC|auto_generated|counter_reg_bit [4] $end
|
|
$var wire 1 N& PC|auto_generated|counter_reg_bit [3] $end
|
|
$var wire 1 O& PC|auto_generated|counter_reg_bit [2] $end
|
|
$var wire 1 P& PC|auto_generated|counter_reg_bit [1] $end
|
|
$var wire 1 Q& PC|auto_generated|counter_reg_bit [0] $end
|
|
$var wire 1 R& inst11|scfifo_component|auto_generated|dpfifo|FIFOram|address_reg_b [0] $end
|
|
$var wire 1 S& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [13] $end
|
|
$var wire 1 T& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [12] $end
|
|
$var wire 1 U& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [11] $end
|
|
$var wire 1 V& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [10] $end
|
|
$var wire 1 W& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9] $end
|
|
$var wire 1 X& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] $end
|
|
$var wire 1 Y& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] $end
|
|
$var wire 1 Z& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] $end
|
|
$var wire 1 [& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] $end
|
|
$var wire 1 \& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] $end
|
|
$var wire 1 ]& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] $end
|
|
$var wire 1 ^& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] $end
|
|
$var wire 1 _& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] $end
|
|
$var wire 1 `& inst11|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0] $end
|
|
$var wire 1 a& inst11|scfifo_component|auto_generated|dpfifo|FIFOram|decode2|eq_node [1] $end
|
|
$var wire 1 b& inst11|scfifo_component|auto_generated|dpfifo|FIFOram|decode2|eq_node [0] $end
|
|
$var wire 1 c& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [13] $end
|
|
$var wire 1 d& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [12] $end
|
|
$var wire 1 e& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [11] $end
|
|
$var wire 1 f& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [10] $end
|
|
$var wire 1 g& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9] $end
|
|
$var wire 1 h& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] $end
|
|
$var wire 1 i& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] $end
|
|
$var wire 1 j& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] $end
|
|
$var wire 1 k& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] $end
|
|
$var wire 1 l& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] $end
|
|
$var wire 1 m& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] $end
|
|
$var wire 1 n& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] $end
|
|
$var wire 1 o& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] $end
|
|
$var wire 1 p& inst11|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0] $end
|
|
$var wire 1 q& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [13] $end
|
|
$var wire 1 r& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [12] $end
|
|
$var wire 1 s& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [11] $end
|
|
$var wire 1 t& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [10] $end
|
|
$var wire 1 u& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] $end
|
|
$var wire 1 v& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $end
|
|
$var wire 1 w& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $end
|
|
$var wire 1 x& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $end
|
|
$var wire 1 y& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $end
|
|
$var wire 1 z& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $end
|
|
$var wire 1 {& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $end
|
|
$var wire 1 |& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $end
|
|
$var wire 1 }& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $end
|
|
$var wire 1 ~& inst11|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $end
|
|
$var wire 1 !' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a24_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 "' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a12_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 #' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a8_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 $' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a28_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 %' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a16_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 &' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a4_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 '' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 (' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a20_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 )' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a25_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 *' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a13_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 +' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a9_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 ,' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a29_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 -' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a17_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 .' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a5_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 /' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a1_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 0' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a21_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 1' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a14_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 2' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a26_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 3' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a10_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 4' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a30_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 5' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a18_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 6' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a6_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 7' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a2_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 8' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a22_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 9' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a15_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 :' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a27_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 ;' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a11_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 <' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a31_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 =' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a19_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 >' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a7_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 ?' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a3_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 @' inst11|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a23_PORTBDATAOUT_bus [0] $end
|
|
$var wire 1 A' RAM|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 B' RAM|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 C' RAM|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 D' RAM|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 E' RAM|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 F' RAM|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 G' RAM|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 H' RAM|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 I' RAM|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 J' RAM|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 K' RAM|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 L' RAM|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 M' RAM|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 N' RAM|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 O' RAM|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0] $end
|
|
$var wire 1 P' RAM|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
#0
|
|
$dumpvars
|
|
1!
|
|
x"
|
|
02
|
|
01
|
|
00
|
|
0/
|
|
0.
|
|
0-
|
|
0,
|
|
0+
|
|
0*
|
|
0)
|
|
0(
|
|
0'
|
|
0&
|
|
0%
|
|
0$
|
|
0#
|
|
16
|
|
05
|
|
04
|
|
03
|
|
07
|
|
0>
|
|
0=
|
|
0<
|
|
0;
|
|
0:
|
|
09
|
|
18
|
|
0?
|
|
0@
|
|
1A
|
|
xB
|
|
1C
|
|
1D
|
|
1E
|
|
0F
|
|
0G
|
|
0H
|
|
0I
|
|
0J
|
|
0K
|
|
0L
|
|
0M
|
|
0N
|
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