$date
	Thu Jul 22 22:29:56 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module friscv_rv32i_testbench $end
$var wire 1 ! inst_rready $end
$var wire 2 " inst_rresp [1:0] $end
$var wire 1 # uart_cts $end
$var wire 1 $ uart_rx $end
$var wire 1 % uart_tx $end
$var wire 1 & uart_rts $end
$var wire 1 ' mem_wr $end
$var wire 32 ( mem_wdata [31:0] $end
$var wire 4 ) mem_strb [3:0] $end
$var wire 1 * mem_ready $end
$var wire 32 + mem_rdata [31:0] $end
$var wire 1 , mem_en $end
$var wire 16 - mem_addr [15:0] $end
$var wire 1 . inst_rvalid $end
$var wire 8 / inst_rid [7:0] $end
$var wire 128 0 inst_rdata [127:0] $end
$var wire 1 1 inst_bvalid $end
$var wire 2 2 inst_bresp [1:0] $end
$var wire 1 3 inst_awready $end
$var wire 1 4 inst_arvalid $end
$var wire 1 5 inst_arready $end
$var wire 3 6 inst_arprot [2:0] $end
$var wire 8 7 inst_arid [7:0] $end
$var wire 16 8 inst_araddr [15:0] $end
$var wire 32 9 gpio_out [31:0] $end
$var wire 1 : ebreak $end
$var reg 1 ; aclk $end
$var reg 1 < aresetn $end
$var reg 1 = enable $end
$var reg 32 > gpio_in [31:0] $end
$var reg 16 ? inst_awaddr [15:0] $end
$var reg 8 @ inst_awid [7:0] $end
$var reg 3 A inst_awprot [2:0] $end
$var reg 1 B inst_awvalid $end
$var reg 1 C inst_bready $end
$var reg 128 D inst_wdata [127:0] $end
$var reg 8 E inst_wid [7:0] $end
$var reg 1 F inst_wready $end
$var reg 1 G inst_wvalid $end
$var reg 1 H srst $end
$var integer 32 I inst_counter [31:0] $end
$var integer 32 J svut_critical [31:0] $end
$var integer 32 K svut_error [31:0] $end
$var integer 32 L svut_error_total [31:0] $end
$var integer 32 M svut_nb_test [31:0] $end
$var integer 32 N svut_nb_test_success [31:0] $end
$var integer 32 O svut_status [31:0] $end
$var integer 32 P svut_test_number [31:0] $end
$var integer 32 Q svut_warning [31:0] $end
$var integer 32 R timer [31:0] $end
$scope module data_ram $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 16 S p2_addr [15:0] $end
$var wire 1 T p2_en $end
$var wire 4 U p2_strb [3:0] $end
$var wire 32 V p2_wdata [31:0] $end
$var wire 1 W p2_wr $end
$var wire 1 H srst $end
$var wire 32 X p2_rdata [31:0] $end
$var wire 1 ' p1_wr $end
$var wire 32 Y p1_wdata [31:0] $end
$var wire 4 Z p1_strb [3:0] $end
$var wire 32 [ p1_rdata [31:0] $end
$var wire 1 , p1_en $end
$var wire 16 \ p1_addr [15:0] $end
$var reg 1 * p1_ready $end
$var reg 1 ] p2_ready $end
$scope begin LATENCY1 $end
$upscope $end
$scope module ram $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 16 ^ p2_addr [15:0] $end
$var wire 1 T p2_en $end
$var wire 4 _ p2_strb [3:0] $end
$var wire 32 ` p2_wdata [31:0] $end
$var wire 1 W p2_wr $end
$var wire 1 H srst $end
$var wire 1 ' p1_wr $end
$var wire 32 a p1_wdata [31:0] $end
$var wire 4 b p1_strb [3:0] $end
$var wire 1 , p1_en $end
$var wire 16 c p1_addr [15:0] $end
$var reg 32 d p1_rdata [31:0] $end
$var reg 32 e p2_rdata [31:0] $end
$scope begin $ivl_for_loop0 $end
$var integer 32 f i [31:0] $end
$upscope $end
$scope begin $ivl_for_loop1 $end
$var integer 32 g i [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module dut $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 1 = enable $end
$var wire 32 h gpio_in [31:0] $end
$var wire 3 i inst_arprot_s [2:0] $end
$var wire 1 ! inst_rready $end
$var wire 2 j inst_rresp [1:0] $end
$var wire 2 k inst_rresp_s [1:0] $end
$var wire 32 l mem_rdata [31:0] $end
$var wire 1 * mem_ready $end
$var wire 4 m proc_fenceinfo [3:0] $end
$var wire 1 H srst $end
$var wire 1 # uart_cts $end
$var wire 1 $ uart_rx $end
$var wire 1 % uart_tx $end
$var wire 1 & uart_rts $end
$var wire 1 n proc_ready $end
$var wire 87 o proc_instbus [86:0] $end
$var wire 1 p proc_en $end
$var wire 1 q proc_empty $end
$var wire 1 r mst_wr $end
$var wire 32 s mst_wdata [31:0] $end
$var wire 4 t mst_strb [3:0] $end
$var wire 1 u mst_ready $end
$var wire 32 v mst_rdata [31:0] $end
$var wire 1 w mst_en $end
$var wire 16 x mst_addr [15:0] $end
$var wire 32 y memfy_rs2_val [31:0] $end
$var wire 5 z memfy_rs2_addr [4:0] $end
$var wire 32 { memfy_rs1_val [31:0] $end
$var wire 5 | memfy_rs1_addr [4:0] $end
$var wire 1 } memfy_rd_wr $end
$var wire 32 ~ memfy_rd_val [31:0] $end
$var wire 4 !" memfy_rd_strb [3:0] $end
$var wire 5 "" memfy_rd_addr [4:0] $end
$var wire 1 ' mem_wr $end
$var wire 32 #" mem_wdata [31:0] $end
$var wire 4 $" mem_strb [3:0] $end
$var wire 1 , mem_en $end
$var wire 16 %" mem_addr [15:0] $end
$var wire 1 &" inst_rvalid_s $end
$var wire 1 . inst_rvalid $end
$var wire 1 '" inst_rready_s $end
$var wire 8 (" inst_rid_s [7:0] $end
$var wire 8 )" inst_rid [7:0] $end
$var wire 32 *" inst_rdata_s [31:0] $end
$var wire 128 +" inst_rdata [127:0] $end
$var wire 1 ," inst_arvalid_s $end
$var wire 1 4 inst_arvalid $end
$var wire 1 -" inst_arready_s $end
$var wire 1 5 inst_arready $end
$var wire 3 ." inst_arprot [2:0] $end
$var wire 8 /" inst_arid_s [7:0] $end
$var wire 8 0" inst_arid [7:0] $end
$var wire 16 1" inst_araddr_s [15:0] $end
$var wire 16 2" inst_araddr [15:0] $end
$var wire 1 3" gpio_wr $end
$var wire 32 4" gpio_wdata [31:0] $end
$var wire 4 5" gpio_strb [3:0] $end
$var wire 1 6" gpio_ready $end
$var wire 32 7" gpio_rdata [31:0] $end
$var wire 32 8" gpio_out [31:0] $end
$var wire 1 9" gpio_en $end
$var wire 16 :" gpio_addr [15:0] $end
$var wire 1 ;" flush_req $end
$var wire 1 <" flush_ack $end
$var wire 1 : ebreak $end
$var wire 32 =" ctrl_rs2_val [31:0] $end
$var wire 5 >" ctrl_rs2_addr [4:0] $end
$var wire 32 ?" ctrl_rs1_val [31:0] $end
$var wire 5 @" ctrl_rs1_addr [4:0] $end
$var wire 1 A" ctrl_rd_wr $end
$var wire 32 B" ctrl_rd_val [31:0] $end
$var wire 5 C" ctrl_rd_addr [4:0] $end
$var wire 32 D" csr_rs1_val [31:0] $end
$var wire 5 E" csr_rs1_addr [4:0] $end
$var wire 1 F" csr_ready $end
$var wire 1 G" csr_rd_wr $end
$var wire 32 H" csr_rd_val [31:0] $end
$var wire 5 I" csr_rd_addr [4:0] $end
$var wire 87 J" csr_instbus [86:0] $end
$var wire 1 K" csr_en $end
$var wire 32 L" alu_rs2_val [31:0] $end
$var wire 5 M" alu_rs2_addr [4:0] $end
$var wire 32 N" alu_rs1_val [31:0] $end
$var wire 5 O" alu_rs1_addr [4:0] $end
$var wire 1 P" alu_rd_wr $end
$var wire 32 Q" alu_rd_val [31:0] $end
$var wire 4 R" alu_rd_strb [3:0] $end
$var wire 5 S" alu_rd_addr [4:0] $end
$scope begin USE_ICACHE $end
$scope module icache $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 3 T" ctrl_arprot [2:0] $end
$var wire 2 U" ctrl_rresp [1:0] $end
$var wire 1 <" flush_ack $end
$var wire 2 V" icache_arburst [1:0] $end
$var wire 4 W" icache_arcache [3:0] $end
$var wire 8 X" icache_arlen [7:0] $end
$var wire 2 Y" icache_arlock [1:0] $end
$var wire 4 Z" icache_arqos [3:0] $end
$var wire 4 [" icache_arregion [3:0] $end
$var wire 3 \" icache_arsize [2:0] $end
$var wire 1 ]" icache_rlast $end
$var wire 1 ! icache_rready $end
$var wire 2 ^" icache_rresp [1:0] $end
$var wire 1 H srst $end
$var wire 1 _" memctrl_arvalid $end
$var wire 1 `" memctrl_arready $end
$var wire 3 a" memctrl_arprot [2:0] $end
$var wire 8 b" memctrl_arid [7:0] $end
$var wire 16 c" memctrl_araddr [15:0] $end
$var wire 1 d" is_flushing $end
$var wire 1 . icache_rvalid $end
$var wire 8 e" icache_rid [7:0] $end
$var wire 128 f" icache_rdata [127:0] $end
$var wire 1 4 icache_arvalid $end
$var wire 1 5 icache_arready $end
$var wire 3 g" icache_arprot [2:0] $end
$var wire 8 h" icache_arid [7:0] $end
$var wire 16 i" icache_araddr [15:0] $end
$var wire 1 ;" flush_req $end
$var wire 1 j" flush_ack_memctrl $end
$var wire 1 k" flush_ack_fetcher $end
$var wire 1 &" ctrl_rvalid $end
$var wire 1 '" ctrl_rready $end
$var wire 8 l" ctrl_rid [7:0] $end
$var wire 32 m" ctrl_rdata [31:0] $end
$var wire 1 ," ctrl_arvalid $end
$var wire 1 -" ctrl_arready $end
$var wire 8 n" ctrl_arid [7:0] $end
$var wire 16 o" ctrl_araddr [15:0] $end
$var wire 1 p" cache_wen $end
$var wire 128 q" cache_wdata [127:0] $end
$var wire 16 r" cache_waddr [15:0] $end
$var wire 1 s" cache_ren $end
$var wire 32 t" cache_rdata [31:0] $end
$var wire 16 u" cache_raddr [15:0] $end
$var wire 1 v" cache_miss $end
$var wire 1 w" cache_hit $end
$scope module cache_lines $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 1 H srst $end
$var wire 3 x" wtag [2:0] $end
$var wire 132 y" wline [131:0] $end
$var wire 9 z" windex [8:0] $end
$var wire 1 p" wen $end
$var wire 128 {" wdata [127:0] $end
$var wire 16 |" waddr [15:0] $end
$var wire 3 }" rtag [2:0] $end
$var wire 1 ~" rset $end
$var wire 2 !# roffset [1:0] $end
$var wire 128 "# rline [127:0] $end
$var wire 9 ## rindex [8:0] $end
$var wire 1 s" ren $end
$var wire 16 $# raddr [15:0] $end
$var wire 1 d" flush $end
$var reg 1 w" hit $end
$var reg 1 v" miss $end
$var reg 32 %# rdata [31:0] $end
$scope begin $ivl_for_loop3 $end
$var integer 32 &# i [31:0] $end
$upscope $end
$upscope $end
$scope module fetcher $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 1 w" cache_hit $end
$var wire 1 v" cache_miss $end
$var wire 32 '# cache_rdata [31:0] $end
$var wire 3 (# ctrl_arprot [2:0] $end
$var wire 32 )# ctrl_rdata [31:0] $end
$var wire 8 *# ctrl_rid [7:0] $end
$var wire 2 +# ctrl_rresp [1:0] $end
$var wire 1 &" ctrl_rvalid $end
$var wire 3 ,# memctrl_arprot [2:0] $end
$var wire 1 H srst $end
$var wire 1 -# reboot $end
$var wire 1 `" memctrl_arready $end
$var wire 1 ;" flush_req $end
$var wire 1 .# fifo_full_mf $end
$var wire 1 /# fifo_full_if $end
$var wire 1 0# fifo_empty_mf $end
$var wire 1 1# fifo_empty_if $end
$var wire 1 '" ctrl_rready $end
$var wire 1 ," ctrl_arvalid $end
$var wire 1 -" ctrl_arready $end
$var wire 8 2# ctrl_arid [7:0] $end
$var wire 16 3# ctrl_araddr [15:0] $end
$var wire 1 p" cache_writing $end
$var wire 8 4# cache_rid [7:0] $end
$var wire 1 s" cache_ren $end
$var wire 16 5# cache_raddr [15:0] $end
$var wire 8 6# arid_mf [7:0] $end
$var wire 8 7# arid_if [7:0] $end
$var wire 16 8# araddr_mf [15:0] $end
$var wire 16 9# araddr_if [15:0] $end
$var reg 16 :# araddr_ffd [15:0] $end
$var reg 8 ;# arid_ffd [7:0] $end
$var reg 8 <# arid_reboot [7:0] $end
$var reg 1 k" flush_ack $end
$var reg 1 =# flush_fifo $end
$var reg 16 ># memctrl_araddr [15:0] $end
$var reg 8 ?# memctrl_arid [7:0] $end
$var reg 1 _" memctrl_arvalid $end
$var reg 1 @# pull_addr_if $end
$var reg 1 A# pull_addr_mf $end
$var reg 3 B# seq [2:0] $end
$scope module if_fifo $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 24 C# data_in [23:0] $end
$var wire 1 D# flush $end
$var wire 1 @# pull $end
$var wire 1 H srst $end
$var wire 1 E# wr_en $end
$var wire 1 ," push $end
$var wire 1 F# pass_thru $end
$var wire 1 G# full_flag $end
$var wire 1 /# full $end
$var wire 1 H# empty_flag $end
$var wire 1 1# empty $end
$var wire 24 I# data_out [23:0] $end
$var wire 24 J# data_fifo [23:0] $end
$var reg 4 K# rdptr [3:0] $end
$var reg 4 L# wrptr [3:0] $end
$scope begin PASS_THRU_MODE $end
$upscope $end
$scope module fifo_ram $end
$var wire 1 ; aclk $end
$var wire 3 M# addr_in [2:0] $end
$var wire 3 N# addr_out [2:0] $end
$var wire 24 O# data_in [23:0] $end
$var wire 1 E# wr_en $end
$var wire 24 P# data_out [23:0] $end
$scope begin genblk2 $end
$upscope $end
$upscope $end
$upscope $end
$scope module mf_fifo $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 24 Q# data_in [23:0] $end
$var wire 1 R# flush $end
$var wire 1 A# pull $end
$var wire 1 v" push $end
$var wire 1 H srst $end
$var wire 1 S# wr_en $end
$var wire 1 T# pass_thru $end
$var wire 1 U# full_flag $end
$var wire 1 .# full $end
$var wire 1 V# empty_flag $end
$var wire 1 0# empty $end
$var wire 24 W# data_out [23:0] $end
$var wire 24 X# data_fifo [23:0] $end
$var reg 2 Y# rdptr [1:0] $end
$var reg 2 Z# wrptr [1:0] $end
$scope begin PASS_THRU_MODE $end
$upscope $end
$scope module fifo_ram $end
$var wire 1 ; aclk $end
$var wire 1 [# addr_in $end
$var wire 1 \# addr_out $end
$var wire 24 ]# data_in [23:0] $end
$var wire 1 S# wr_en $end
$var wire 24 ^# data_out [23:0] $end
$scope begin genblk2 $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module mem_ctrl $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 128 _# cache_wdata [127:0] $end
$var wire 16 `# ctrl_araddr [15:0] $end
$var wire 8 a# ctrl_arid [7:0] $end
$var wire 3 b# ctrl_arprot [2:0] $end
$var wire 1 `" ctrl_arready $end
$var wire 1 _" ctrl_arvalid $end
$var wire 16 c# mem_araddr [15:0] $end
$var wire 2 d# mem_arburst [1:0] $end
$var wire 4 e# mem_arcache [3:0] $end
$var wire 8 f# mem_arid [7:0] $end
$var wire 8 g# mem_arlen [7:0] $end
$var wire 2 h# mem_arlock [1:0] $end
$var wire 3 i# mem_arprot [2:0] $end
$var wire 4 j# mem_arqos [3:0] $end
$var wire 4 k# mem_arregion [3:0] $end
$var wire 3 l# mem_arsize [2:0] $end
$var wire 1 4 mem_arvalid $end
$var wire 1 ]" mem_rlast $end
$var wire 1 ! mem_rready $end
$var wire 2 m# mem_rresp [1:0] $end
$var wire 1 H srst $end
$var wire 1 . mem_rvalid $end
$var wire 8 n# mem_rid [7:0] $end
$var wire 128 o# mem_rdata [127:0] $end
$var wire 1 5 mem_arready $end
$var wire 1 ;" flush_req $end
$var wire 1 p" cache_wen $end
$var wire 16 p# cache_waddr [15:0] $end
$var reg 2 q# cfsm [1:0] $end
$var reg 17 r# erase_addr [16:0] $end
$var reg 1 s# erase_wen $end
$var reg 1 d" flush $end
$var reg 1 j" flush_ack $end
$upscope $end
$upscope $end
$upscope $end
$scope module control $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 3 t# arprot [2:0] $end
$var wire 1 -" arready $end
$var wire 1 K" csr_en $end
$var wire 87 u# csr_instbus [86:0] $end
$var wire 5 v# ctrl_rd_addr [4:0] $end
$var wire 5 w# ctrl_rs1_addr [4:0] $end
$var wire 5 x# ctrl_rs2_addr [4:0] $end
$var wire 1 <" flush_ack $end
$var wire 1 y# jump_branch $end
$var wire 1 p proc_en $end
$var wire 4 z# proc_fenceinfo [3:0] $end
$var wire 1 {# push_inst $end
$var wire 32 |# rdata [31:0] $end
$var wire 8 }# rid [7:0] $end
$var wire 1 '" rready $end
$var wire 2 ~# rresp [1:0] $end
$var wire 1 &" rvalid $end
$var wire 1 H srst $end
$var wire 5 !$ zimm [4:0] $end
$var wire 4 "$ succ [3:0] $end
$var wire 6 #$ shamt [5:0] $end
$var wire 5 $$ rs2 [4:0] $end
$var wire 5 %$ rs1 [4:0] $end
$var wire 5 &$ rd [4:0] $end
$var wire 1 '$ pull_inst $end
$var wire 1 ($ processing $end
$var wire 1 n proc_ready $end
$var wire 87 )$ proc_instbus [86:0] $end
$var wire 1 q proc_empty $end
$var wire 4 *$ pred [3:0] $end
$var wire 32 +$ pc_plus4 [31:0] $end
$var wire 32 ,$ pc_jalr [31:0] $end
$var wire 32 -$ pc_jal [31:0] $end
$var wire 32 .$ pc_branching [31:0] $end
$var wire 32 /$ pc_auipc [31:0] $end
$var wire 32 0$ pc [31:0] $end
$var wire 7 1$ opcode [6:0] $end
$var wire 1 2$ lui $end
$var wire 1 3$ jalr $end
$var wire 1 4$ jal $end
$var wire 32 5$ instruction [31:0] $end
$var wire 1 6$ inst_error $end
$var wire 20 7$ imm20 [19:0] $end
$var wire 12 8$ imm12 [11:0] $end
$var wire 1 9$ goto_branch $end
$var wire 7 :$ funct7 [6:0] $end
$var wire 3 ;$ funct3 [2:0] $end
$var wire 1 <$ fifo_full $end
$var wire 1 =$ fifo_empty $end
$var wire 2 >$ fence [1:0] $end
$var wire 3 ?$ env [2:0] $end
$var wire 32 @$ ctrl_rs2_val [31:0] $end
$var wire 32 A$ ctrl_rs1_val [31:0] $end
$var wire 1 A" ctrl_rd_wr $end
$var wire 32 B$ ctrl_rd_val [31:0] $end
$var wire 1 F" csr_ready $end
$var wire 12 C$ csr [11:0] $end
$var wire 1 D$ cant_process_now $end
$var wire 1 E$ cant_branch_now $end
$var wire 1 F$ branching $end
$var wire 1 G$ bne $end
$var wire 1 H$ bltu $end
$var wire 1 I$ blt $end
$var wire 1 J$ bgeu $end
$var wire 1 K$ bge $end
$var wire 1 L$ beq $end
$var wire 1 M$ auipc $end
$var reg 16 N$ araddr [15:0] $end
$var reg 8 O$ arid [7:0] $end
$var reg 1 ," arvalid $end
$var reg 4 P$ cfsm [3:0] $end
$var reg 1 : ebreak $end
$var reg 1 Q$ flush_fifo $end
$var reg 1 ;" flush_req $end
$var reg 32 R$ pc_auipc_saved [31:0] $end
$var reg 32 S$ pc_jal_saved [31:0] $end
$var reg 32 T$ pc_reg [31:0] $end
$scope module decoder $end
$var wire 32 U$ instruction [31:0] $end
$var reg 1 M$ auipc $end
$var reg 1 F$ branching $end
$var reg 12 V$ csr [11:0] $end
$var reg 3 W$ env [2:0] $end
$var reg 2 X$ fence [1:0] $end
$var reg 3 Y$ funct3 [2:0] $end
$var reg 7 Z$ funct7 [6:0] $end
$var reg 12 [$ imm12 [11:0] $end
$var reg 20 \$ imm20 [19:0] $end
$var reg 1 6$ inst_error $end
$var reg 1 4$ jal $end
$var reg 1 3$ jalr $end
$var reg 1 2$ lui $end
$var reg 7 ]$ opcode [6:0] $end
$var reg 4 ^$ pred [3:0] $end
$var reg 1 ($ processing $end
$var reg 5 _$ rd [4:0] $end
$var reg 5 `$ rs1 [4:0] $end
$var reg 5 a$ rs2 [4:0] $end
$var reg 6 b$ shamt [5:0] $end
$var reg 4 c$ succ [3:0] $end
$var reg 5 d$ zimm [4:0] $end
$upscope $end
$scope module inst_fifo $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 32 e$ data_in [31:0] $end
$var wire 1 Q$ flush $end
$var wire 1 f$ pass_thru $end
$var wire 1 '$ pull $end
$var wire 1 {# push $end
$var wire 1 H srst $end
$var wire 1 g$ wr_en $end
$var wire 1 h$ full_flag $end
$var wire 1 <$ full $end
$var wire 1 i$ empty_flag $end
$var wire 1 =$ empty $end
$var wire 32 j$ data_out [31:0] $end
$var wire 32 k$ data_fifo [31:0] $end
$var reg 4 l$ rdptr [3:0] $end
$var reg 4 m$ wrptr [3:0] $end
$scope begin STORE_MODE $end
$upscope $end
$scope module fifo_ram $end
$var wire 1 ; aclk $end
$var wire 3 n$ addr_in [2:0] $end
$var wire 3 o$ addr_out [2:0] $end
$var wire 32 p$ data_in [31:0] $end
$var wire 1 g$ wr_en $end
$var wire 32 q$ data_out [31:0] $end
$scope begin genblk2 $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module csrs $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 87 r$ instbus [86:0] $end
$var wire 5 s$ rs1_addr [4:0] $end
$var wire 1 H srst $end
$var wire 1 K" valid $end
$var wire 5 t$ zimm [4:0] $end
$var wire 6 u$ shamt [5:0] $end
$var wire 5 v$ rs2 [4:0] $end
$var wire 32 w$ rs1_val [31:0] $end
$var wire 5 x$ rs1 [4:0] $end
$var wire 5 y$ rd [4:0] $end
$var wire 7 z$ opcode [6:0] $end
$var wire 20 {$ imm20 [19:0] $end
$var wire 12 |$ imm12 [11:0] $end
$var wire 7 }$ funct7 [6:0] $end
$var wire 3 ~$ funct3 [2:0] $end
$var wire 1 !% csr_rd $end
$var wire 12 "% csr [11:0] $end
$var reg 2 #% cfsm [1:0] $end
$var reg 12 $% csr_r [11:0] $end
$var reg 1 %% csr_wr $end
$var reg 3 &% funct3_r [2:0] $end
$var reg 32 '% newval [31:0] $end
$var reg 32 (% oldval [31:0] $end
$var reg 5 )% rd_wr_addr [4:0] $end
$var reg 1 G" rd_wr_en $end
$var reg 32 *% rd_wr_val [31:0] $end
$var reg 1 F" ready $end
$var reg 5 +% rs1_addr_r [4:0] $end
$var reg 32 ,% rs1_val_r [31:0] $end
$var reg 5 -% zimm_r [4:0] $end
$scope begin $ivl_for_loop2 $end
$var integer 32 .% i [31:0] $end
$upscope $end
$upscope $end
$scope module ios $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 32 /% gpio_in [31:0] $end
$var wire 1 H srst $end
$var wire 1 # uart_cts $end
$var wire 1 $ uart_rx $end
$var wire 1 % uart_tx $end
$var wire 1 & uart_rts $end
$var wire 1 0% slv1_wr $end
$var wire 32 1% slv1_wdata [31:0] $end
$var wire 4 2% slv1_strb [3:0] $end
$var wire 1 3% slv1_ready $end
$var wire 32 4% slv1_rdata [31:0] $end
$var wire 1 5% slv1_en $end
$var wire 16 6% slv1_addr [15:0] $end
$var wire 1 7% slv0_wr $end
$var wire 32 8% slv0_wdata [31:0] $end
$var wire 4 9% slv0_strb [3:0] $end
$var wire 1 :% slv0_ready $end
$var wire 32 ;% slv0_rdata [31:0] $end
$var wire 1 <% slv0_en $end
$var wire 16 =% slv0_addr [15:0] $end
$var wire 1 3" mst_wr $end
$var wire 32 >% mst_wdata [31:0] $end
$var wire 4 ?% mst_strb [3:0] $end
$var wire 1 6" mst_ready $end
$var wire 32 @% mst_rdata [31:0] $end
$var wire 1 w mst_en $end
$var wire 16 A% mst_addr [15:0] $end
$var wire 32 B% gpio_out [31:0] $end
$scope module apb_interconnect $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 1 H srst $end
$var wire 1 3% slv1_ready $end
$var wire 32 C% slv1_rdata [31:0] $end
$var wire 1 :% slv0_ready $end
$var wire 32 D% slv0_rdata [31:0] $end
$var wire 1 3" mst_wr $end
$var wire 32 E% mst_wdata [31:0] $end
$var wire 4 F% mst_strb [3:0] $end
$var wire 1 w mst_en $end
$var wire 16 G% mst_addr [15:0] $end
$var reg 32 H% mst_rdata [31:0] $end
$var reg 1 6" mst_ready $end
$var reg 16 I% slv0_addr [15:0] $end
$var reg 1 <% slv0_en $end
$var reg 4 J% slv0_strb [3:0] $end
$var reg 32 K% slv0_wdata [31:0] $end
$var reg 1 7% slv0_wr $end
$var reg 16 L% slv1_addr [15:0] $end
$var reg 1 5% slv1_en $end
$var reg 4 M% slv1_strb [3:0] $end
$var reg 32 N% slv1_wdata [31:0] $end
$var reg 1 0% slv1_wr $end
$upscope $end
$scope module gpios $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 32 O% gpio_in [31:0] $end
$var wire 32 P% gpio_out [31:0] $end
$var wire 16 Q% mst_addr [15:0] $end
$var wire 1 <% mst_en $end
$var wire 4 R% mst_strb [3:0] $end
$var wire 32 S% mst_wdata [31:0] $end
$var wire 1 7% mst_wr $end
$var wire 32 T% register1 [31:0] $end
$var wire 1 H srst $end
$var reg 32 U% mst_rdata [31:0] $end
$var reg 1 :% mst_ready $end
$var reg 32 V% register0 [31:0] $end
$upscope $end
$scope module uart $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 1 W% busy $end
$var wire 16 X% mst_addr [15:0] $end
$var wire 1 5% mst_en $end
$var wire 4 Y% mst_strb [3:0] $end
$var wire 32 Z% mst_wdata [31:0] $end
$var wire 1 0% mst_wr $end
$var wire 1 H srst $end
$var wire 1 # uart_cts $end
$var wire 1 & uart_rts $end
$var wire 1 $ uart_rx $end
$var wire 1 [% uart_rx_sync $end
$var wire 1 \% tx_full $end
$var wire 1 ]% tx_empty $end
$var wire 8 ^% tx_data [7:0] $end
$var wire 1 _% rx_full $end
$var wire 1 `% rx_empty $end
$var wire 8 a% register3 [7:0] $end
$var wire 32 b% register0 [31:0] $end
$var reg 16 c% clock_divider [15:0] $end
$var reg 1 d% enable $end
$var reg 1 e% loopback_mode $end
$var reg 32 f% mst_rdata [31:0] $end
$var reg 1 3% mst_ready $end
$var reg 1 g% parity_en $end
$var reg 1 h% parity_mode $end
$var reg 8 i% register2 [7:0] $end
$var reg 16 j% rx_baud_cnt [15:0] $end
$var reg 4 k% rx_bit_cnt [3:0] $end
$var reg 8 l% rx_data [7:0] $end
$var reg 1 m% rx_pull $end
$var reg 1 n% rx_push $end
$var reg 4 o% rxfsm [3:0] $end
$var reg 1 p% stop_mode $end
$var reg 16 q% tx_baud_cnt [15:0] $end
$var reg 4 r% tx_bit_cnt [3:0] $end
$var reg 8 s% tx_data_srr [7:0] $end
$var reg 1 t% tx_pull $end
$var reg 1 u% tx_push $end
$var reg 4 v% txfsm [3:0] $end
$var reg 2 w% uart_rx_cdc [1:0] $end
$var reg 1 % uart_tx $end
$scope module rx_fifo $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 8 x% data_in [7:0] $end
$var wire 1 y% flush $end
$var wire 1 z% pass_thru $end
$var wire 1 m% pull $end
$var wire 1 n% push $end
$var wire 1 H srst $end
$var wire 1 {% wr_en $end
$var wire 1 |% full_flag $end
$var wire 1 _% full $end
$var wire 1 }% empty_flag $end
$var wire 1 `% empty $end
$var wire 8 ~% data_out [7:0] $end
$var wire 8 !& data_fifo [7:0] $end
$var reg 3 "& rdptr [2:0] $end
$var reg 3 #& wrptr [2:0] $end
$scope begin STORE_MODE $end
$upscope $end
$scope module fifo_ram $end
$var wire 1 ; aclk $end
$var wire 2 $& addr_in [1:0] $end
$var wire 2 %& addr_out [1:0] $end
$var wire 8 && data_in [7:0] $end
$var wire 1 {% wr_en $end
$var wire 8 '& data_out [7:0] $end
$scope begin genblk2 $end
$upscope $end
$upscope $end
$upscope $end
$scope module tx_fifo $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 8 (& data_in [7:0] $end
$var wire 1 )& flush $end
$var wire 1 *& pass_thru $end
$var wire 1 t% pull $end
$var wire 1 u% push $end
$var wire 1 H srst $end
$var wire 1 +& wr_en $end
$var wire 1 ,& full_flag $end
$var wire 1 \% full $end
$var wire 1 -& empty_flag $end
$var wire 1 ]% empty $end
$var wire 8 .& data_out [7:0] $end
$var wire 8 /& data_fifo [7:0] $end
$var reg 3 0& rdptr [2:0] $end
$var reg 3 1& wrptr [2:0] $end
$scope begin STORE_MODE $end
$upscope $end
$scope module fifo_ram $end
$var wire 1 ; aclk $end
$var wire 2 2& addr_in [1:0] $end
$var wire 2 3& addr_out [1:0] $end
$var wire 8 4& data_in [7:0] $end
$var wire 1 +& wr_en $end
$var wire 8 5& data_out [7:0] $end
$scope begin genblk2 $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module isa_registers $end
$var wire 1 ; aclk $end
$var wire 32 6& alu_rs1_val [31:0] $end
$var wire 32 7& alu_rs2_val [31:0] $end
$var wire 1 < aresetn $end
$var wire 5 8& csr_rd_addr [4:0] $end
$var wire 32 9& csr_rd_val [31:0] $end
$var wire 1 G" csr_rd_wr $end
$var wire 5 :& csr_rs1_addr [4:0] $end
$var wire 32 ;& csr_rs1_val [31:0] $end
$var wire 5 <& ctrl_rd_addr [4:0] $end
$var wire 32 =& ctrl_rd_val [31:0] $end
$var wire 1 A" ctrl_rd_wr $end
$var wire 5 >& ctrl_rs1_addr [4:0] $end
$var wire 32 ?& ctrl_rs1_val [31:0] $end
$var wire 5 @& ctrl_rs2_addr [4:0] $end
$var wire 32 A& ctrl_rs2_val [31:0] $end
$var wire 32 B& memfy_rs1_val [31:0] $end
$var wire 32 C& memfy_rs2_val [31:0] $end
$var wire 1 H srst $end
$var wire 32 D& x0 [31:0] $end
$var wire 32 E& x1 [31:0] $end
$var wire 32 F& x10 [31:0] $end
$var wire 32 G& x11 [31:0] $end
$var wire 32 H& x12 [31:0] $end
$var wire 32 I& x13 [31:0] $end
$var wire 32 J& x14 [31:0] $end
$var wire 32 K& x15 [31:0] $end
$var wire 32 L& x16 [31:0] $end
$var wire 32 M& x17 [31:0] $end
$var wire 32 N& x18 [31:0] $end
$var wire 32 O& x19 [31:0] $end
$var wire 32 P& x2 [31:0] $end
$var wire 32 Q& x20 [31:0] $end
$var wire 32 R& x21 [31:0] $end
$var wire 32 S& x22 [31:0] $end
$var wire 32 T& x23 [31:0] $end
$var wire 32 U& x24 [31:0] $end
$var wire 32 V& x25 [31:0] $end
$var wire 32 W& x26 [31:0] $end
$var wire 32 X& x27 [31:0] $end
$var wire 32 Y& x28 [31:0] $end
$var wire 32 Z& x29 [31:0] $end
$var wire 32 [& x3 [31:0] $end
$var wire 32 \& x30 [31:0] $end
$var wire 32 ]& x31 [31:0] $end
$var wire 32 ^& x4 [31:0] $end
$var wire 32 _& x5 [31:0] $end
$var wire 32 `& x6 [31:0] $end
$var wire 32 a& x7 [31:0] $end
$var wire 32 b& x8 [31:0] $end
$var wire 32 c& x9 [31:0] $end
$var wire 5 d& memfy_rs2_addr [4:0] $end
$var wire 5 e& memfy_rs1_addr [4:0] $end
$var wire 1 } memfy_rd_wr $end
$var wire 32 f& memfy_rd_val [31:0] $end
$var wire 4 g& memfy_rd_strb [3:0] $end
$var wire 5 h& memfy_rd_addr [4:0] $end
$var wire 5 i& alu_rs2_addr [4:0] $end
$var wire 5 j& alu_rs1_addr [4:0] $end
$var wire 1 P" alu_rd_wr $end
$var wire 32 k& alu_rd_val [31:0] $end
$var wire 4 l& alu_rd_strb [3:0] $end
$var wire 5 m& alu_rd_addr [4:0] $end
$var integer 32 n& s [31:0] $end
$scope begin RegisterGeneration[0] $end
$upscope $end
$scope begin RegisterGeneration[1] $end
$upscope $end
$scope begin RegisterGeneration[2] $end
$upscope $end
$scope begin RegisterGeneration[3] $end
$upscope $end
$scope begin RegisterGeneration[4] $end
$upscope $end
$scope begin RegisterGeneration[5] $end
$upscope $end
$scope begin RegisterGeneration[6] $end
$upscope $end
$scope begin RegisterGeneration[7] $end
$upscope $end
$scope begin RegisterGeneration[8] $end
$upscope $end
$scope begin RegisterGeneration[9] $end
$upscope $end
$scope begin RegisterGeneration[10] $end
$upscope $end
$scope begin RegisterGeneration[11] $end
$upscope $end
$scope begin RegisterGeneration[12] $end
$upscope $end
$scope begin RegisterGeneration[13] $end
$upscope $end
$scope begin RegisterGeneration[14] $end
$upscope $end
$scope begin RegisterGeneration[15] $end
$upscope $end
$scope begin RegisterGeneration[16] $end
$upscope $end
$scope begin RegisterGeneration[17] $end
$upscope $end
$scope begin RegisterGeneration[18] $end
$upscope $end
$scope begin RegisterGeneration[19] $end
$upscope $end
$scope begin RegisterGeneration[20] $end
$upscope $end
$scope begin RegisterGeneration[21] $end
$upscope $end
$scope begin RegisterGeneration[22] $end
$upscope $end
$scope begin RegisterGeneration[23] $end
$upscope $end
$scope begin RegisterGeneration[24] $end
$upscope $end
$scope begin RegisterGeneration[25] $end
$upscope $end
$scope begin RegisterGeneration[26] $end
$upscope $end
$scope begin RegisterGeneration[27] $end
$upscope $end
$scope begin RegisterGeneration[28] $end
$upscope $end
$scope begin RegisterGeneration[29] $end
$upscope $end
$scope begin RegisterGeneration[30] $end
$upscope $end
$scope begin RegisterGeneration[31] $end
$upscope $end
$upscope $end
$scope module mem_router $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 32 o& data_mem_rdata [31:0] $end
$var wire 1 * data_mem_ready $end
$var wire 32 p& gpio_rdata [31:0] $end
$var wire 1 6" gpio_ready $end
$var wire 1 H srst $end
$var wire 1 r mst_wr $end
$var wire 32 q& mst_wdata [31:0] $end
$var wire 4 r& mst_strb [3:0] $end
$var wire 1 w mst_en $end
$var wire 16 s& mst_addr [15:0] $end
$var reg 16 t& data_mem_addr [15:0] $end
$var reg 1 , data_mem_en $end
$var reg 4 u& data_mem_strb [3:0] $end
$var reg 32 v& data_mem_wdata [31:0] $end
$var reg 1 ' data_mem_wr $end
$var reg 16 w& gpio_addr [15:0] $end
$var reg 1 9" gpio_en $end
$var reg 4 x& gpio_strb [3:0] $end
$var reg 32 y& gpio_wdata [31:0] $end
$var reg 1 3" gpio_wr $end
$var reg 32 z& mst_rdata [31:0] $end
$var reg 1 u mst_ready $end
$upscope $end
$scope module processing $end
$var wire 1 ; aclk $end
$var wire 1 {& alu_empty $end
$var wire 1 |& alu_en $end
$var wire 1 }& alu_ready $end
$var wire 32 ~& alu_rs1_val [31:0] $end
$var wire 32 !' alu_rs2_val [31:0] $end
$var wire 1 < aresetn $end
$var wire 32 "' mem_rdata [31:0] $end
$var wire 1 u mem_ready $end
$var wire 1 #' memfy_empty $end
$var wire 1 $' memfy_en $end
$var wire 32 %' memfy_rs1_val [31:0] $end
$var wire 32 &' memfy_rs2_val [31:0] $end
$var wire 1 q proc_empty $end
$var wire 1 p proc_en $end
$var wire 4 '' proc_fenceinfo [3:0] $end
$var wire 87 (' proc_instbus [86:0] $end
$var wire 1 n proc_ready $end
$var wire 1 H srst $end
$var wire 5 )' memfy_rs2_addr [4:0] $end
$var wire 5 *' memfy_rs1_addr [4:0] $end
$var wire 1 +' memfy_ready $end
$var wire 1 } memfy_rd_wr $end
$var wire 32 ,' memfy_rd_val [31:0] $end
$var wire 4 -' memfy_rd_strb [3:0] $end
$var wire 5 .' memfy_rd_addr [4:0] $end
$var wire 1 r mem_wr $end
$var wire 32 /' mem_wdata [31:0] $end
$var wire 4 0' mem_strb [3:0] $end
$var wire 1 w mem_en $end
$var wire 16 1' mem_addr [15:0] $end
$var wire 5 2' alu_rs2_addr [4:0] $end
$var wire 5 3' alu_rs1_addr [4:0] $end
$var wire 1 P" alu_rd_wr $end
$var wire 32 4' alu_rd_val [31:0] $end
$var wire 4 5' alu_rd_strb [3:0] $end
$var wire 5 6' alu_rd_addr [4:0] $end
$scope module alu $end
$var wire 32 7' _and [31:0] $end
$var wire 32 8' _andi [31:0] $end
$var wire 32 9' _or [31:0] $end
$var wire 32 :' _ori [31:0] $end
$var wire 32 ;' _xor [31:0] $end
$var wire 32 <' _xori [31:0] $end
$var wire 1 ; aclk $end
$var wire 1 {& alu_empty $end
$var wire 1 |& alu_en $end
$var wire 87 =' alu_instbus [86:0] $end
$var wire 5 >' alu_rd_addr [4:0] $end
$var wire 1 P" alu_rd_wr $end
$var wire 1 }& alu_ready $end
$var wire 5 ?' alu_rs1_addr [4:0] $end
$var wire 32 @' alu_rs1_val [31:0] $end
$var wire 5 A' alu_rs2_addr [4:0] $end
$var wire 32 B' alu_rs2_val [31:0] $end
$var wire 1 < aresetn $end
$var wire 1 H srst $end
$var wire 5 C' zimm [4:0] $end
$var wire 6 D' shamt [5:0] $end
$var wire 5 E' rs2 [4:0] $end
$var wire 5 F' rs1 [4:0] $end
$var wire 5 G' rd [4:0] $end
$var wire 1 H' r_i_opcode $end
$var wire 7 I' opcode [6:0] $end
$var wire 20 J' imm20 [19:0] $end
$var wire 12 K' imm12 [11:0] $end
$var wire 7 L' funct7 [6:0] $end
$var wire 3 M' funct3 [2:0] $end
$var wire 12 N' csr [11:0] $end
$var wire 32 O' alu_rd_val [31:0] $end
$var wire 4 P' alu_rd_strb [3:0] $end
$var wire 32 Q' _sub [31:0] $end
$var wire 32 R' _srli [31:0] $end
$var wire 32 S' _srl [31:0] $end
$var wire 32 T' _srai [31:0] $end
$var wire 32 U' _sra [31:0] $end
$var wire 32 V' _sltu [31:0] $end
$var wire 32 W' _sltiu [31:0] $end
$var wire 32 X' _slti [31:0] $end
$var wire 32 Y' _slt [31:0] $end
$var wire 32 Z' _slli [31:0] $end
$var wire 32 [' _sll [31:0] $end
$var wire 32 \' _addi [31:0] $end
$var wire 32 ]' _add [31:0] $end
$upscope $end
$scope module memfy $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 32 ^' mem_rdata [31:0] $end
$var wire 1 u mem_ready $end
$var wire 1 #' memfy_empty $end
$var wire 1 $' memfy_en $end
$var wire 4 _' memfy_fenceinfo [3:0] $end
$var wire 87 `' memfy_instbus [86:0] $end
$var wire 5 a' memfy_rd_addr [4:0] $end
$var wire 5 b' memfy_rs1_addr [4:0] $end
$var wire 32 c' memfy_rs1_val [31:0] $end
$var wire 5 d' memfy_rs2_addr [4:0] $end
$var wire 32 e' memfy_rs2_val [31:0] $end
$var wire 1 H srst $end
$var wire 5 f' zimm [4:0] $end
$var wire 6 g' shamt [5:0] $end
$var wire 5 h' rs2 [4:0] $end
$var wire 5 i' rs1 [4:0] $end
$var wire 5 j' rd [4:0] $end
$var wire 7 k' opcode [6:0] $end
$var wire 1 } memfy_rd_wr $end
$var wire 32 l' memfy_rd_val [31:0] $end
$var wire 4 m' memfy_rd_strb [3:0] $end
$var wire 1 n' mem_access $end
$var wire 1 o' is_unaligned $end
$var wire 20 p' imm20 [19:0] $end
$var wire 12 q' imm12 [11:0] $end
$var wire 7 r' funct7 [6:0] $end
$var wire 3 s' funct3 [2:0] $end
$var wire 12 t' csr [11:0] $end
$var wire 32 u' addr [31:0] $end
$var reg 3 v' funct3_r [2:0] $end
$var reg 16 w' mem_addr [15:0] $end
$var reg 1 w mem_en $end
$var reg 4 x' mem_strb [3:0] $end
$var reg 32 y' mem_wdata [31:0] $end
$var reg 1 r mem_wr $end
$var reg 1 +' memfy_ready $end
$var reg 4 z' next_strb [3:0] $end
$var reg 2 {' offset [1:0] $end
$var reg 7 |' opcode_r [6:0] $end
$var reg 5 }' rd_r [4:0] $end
$var reg 1 ~' two_phases $end
$scope function aligned_strb $end
$upscope $end
$scope function get_aligned_mem_data $end
$upscope $end
$scope function get_aligned_rd_data $end
$upscope $end
$scope function get_mem_strb $end
$upscope $end
$scope function get_rd_strb $end
$upscope $end
$scope function get_rd_val $end
$upscope $end
$upscope $end
$upscope $end
$scope module statistic $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 1 !( debug $end
$var wire 1 = enable $end
$var wire 1 4 inst_en $end
$var wire 1 H srst $end
$var wire 1 5 inst_ready $end
$var reg 32 "( inst_served [31:0] $end
$var reg 32 #( inst_wait [31:0] $end
$var reg 32 $( uptime [31:0] $end
$upscope $end
$upscope $end
$scope module inst_axi4l_ram $end
$var wire 1 ; aclk $end
$var wire 16 %( araddr [15:0] $end
$var wire 1 < aresetn $end
$var wire 8 &( arid [7:0] $end
$var wire 3 '( arprot [2:0] $end
$var wire 1 5 arready $end
$var wire 1 4 arvalid $end
$var wire 16 (( awaddr [15:0] $end
$var wire 8 )( awid [7:0] $end
$var wire 3 *( awprot [2:0] $end
$var wire 1 B awvalid $end
$var wire 1 C bready $end
$var wire 1 +( raddr_pull $end
$var wire 8 ,( rid [7:0] $end
$var wire 1 ! rready $end
$var wire 2 -( rresp [1:0] $end
$var wire 1 H srst $end
$var wire 128 .( wdata [127:0] $end
$var wire 8 /( wid [7:0] $end
$var wire 1 F wready $end
$var wire 1 G wvalid $end
$var wire 128 0( rdata [127:0] $end
$var wire 1 1( raddr_full $end
$var wire 1 2( raddr_empty $end
$var wire 8 3( arid_s [7:0] $end
$var wire 16 4( araddr_s [15:0] $end
$var reg 1 3 awready $end
$var reg 2 5( bresp [1:0] $end
$var reg 1 1 bvalid $end
$var reg 1 . rvalid $end
$var integer 32 6( random [31:0] $end
$var integer 32 7( rcounter [31:0] $end
$scope module arch_fifo $end
$var wire 1 ; aclk $end
$var wire 1 < aresetn $end
$var wire 24 8( data_in [23:0] $end
$var wire 1 9( flush $end
$var wire 1 :( pass_thru $end
$var wire 1 +( pull $end
$var wire 1 4 push $end
$var wire 1 H srst $end
$var wire 1 ;( wr_en $end
$var wire 1 <( full_flag $end
$var wire 1 1( full $end
$var wire 1 =( empty_flag $end
$var wire 1 2( empty $end
$var wire 24 >( data_out [23:0] $end
$var wire 24 ?( data_fifo [23:0] $end
$var reg 4 @( rdptr [3:0] $end
$var reg 4 A( wrptr [3:0] $end
$scope begin STORE_MODE $end
$upscope $end
$scope module fifo_ram $end
$var wire 1 ; aclk $end
$var wire 3 B( addr_in [2:0] $end
$var wire 3 C( addr_out [2:0] $end
$var wire 24 D( data_in [23:0] $end
$var wire 1 ;( wr_en $end
$var wire 24 E( data_out [23:0] $end
$scope begin genblk2 $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope task run $end
$var reg 1 F( msg $end
$upscope $end
$scope task setup $end
$var reg 1 G( msg $end
$upscope $end
$scope task teardown $end
$var reg 1 H( msg $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
xH(
0G(
0F(
bx E(
b0 D(
b0 C(
b0 B(
b0 A(
b0 @(
bx ?(
bx >(
1=(
0<(
0;(
0:(
09(
b0 8(
b0 7(
b1 6(
bx 5(
bx 4(
bx 3(
12(
01(
bx 0(
bx /(
bx .(
b0 -(
bx ,(
0+(
bx *(
bx )(
bx ((
b0 '(
b0 &(
b0 %(
b0 $(
b0 #(
b0 "(
0!(
0~'
b0 }'
b0 |'
b0 {'
b0 z'
b0 y'
b0 x'
b0 w'
b0 v'
bx u'
bx t'
bx s'
bx r'
bx q'
bx p'
xo'
xn'
b1 m'
b0 l'
bx k'
bx j'
bx i'
bx h'
bx g'
bx f'
bx e'
bx d'
bx c'
bx b'
b0 a'
bx `'
b0 _'
b0 ^'
bx ]'
bx \'
bx ['
bx Z'
b0x Y'
b0x X'
b0x W'
b0x V'
bx U'
bx T'
bx S'
bx R'
bx Q'
bx P'
bx O'
bx N'
bx M'
bx L'
bx K'
bx J'
bx I'
xH'
bx G'
bx F'
bx E'
bx D'
bx C'
bx B'
bx A'
bx @'
bx ?'
bx >'
bx ='
bx <'
bx ;'
bx :'
bx 9'
bx 8'
bx 7'
bx 6'
bx 5'
bx 4'
bx 3'
bx 2'
b0 1'
b0 0'
b0 /'
b0 .'
b1 -'
b0 ,'
0+'
bx *'
bx )'
bx ('
b0 ''
bx &'
bx %'
0$'
1#'
b0 "'
bx !'
bx ~&
1}&
0|&
0{&
b0 z&
b0 y&
b0 x&
b0 w&
b0 v&
b0 u&
b0 t&
b0 s&
b0 r&
b0 q&
b0 p&
bx o&
bx n&
bx m&
bx l&
bx k&
bx j&
bx i&
b0 h&
b1 g&
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bx e&
bx d&
b0 c&
b0 b&
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b0 `&
b0 _&
b0 ^&
b0 ]&
b0 \&
b0 [&
b0 Z&
b0 Y&
b0 X&
b0 W&
b0 V&
b0 U&
b0 T&
b0 S&
b0 R&
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b0 L&
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b0 J&
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b0 H&
b0 G&
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bx C&
bx B&
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bx @&
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bx000000000000 =&
bx <&
bx ;&
bx :&
b0 9&
b0 8&
bx 7&
bx 6&
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b0 4&
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b0 2&
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bx /&
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1-&
0,&
0+&
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bx '&
b0 &&
b0 %&
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bx !&
bx ~%
1}%
0|%
0{%
0z%
0y%
b0 x%
b0 w%
b0 v%
0u%
0t%
b0 s%
b0 r%
b0 q%
0p%
b0 o%
0n%
0m%
b0 l%
b0 k%
b0 j%
b0 i%
0h%
0g%
b0 f%
0e%
0d%
b100 c%
b110101000000000 b%
bx a%
1`%
0_%
bx ^%
1]%
0\%
0[%
b0 Z%
b0 Y%
b0 X%
0W%
b0 V%
b0 U%
bx T%
b0 S%
b0 R%
b0 Q%
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bx O%
b0 N%
b0 M%
b0 L%
b0 K%
b0 J%
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b0 H%
b0 G%
b0 F%
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b0 D%
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b0 B%
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07%
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00%
bx /%
b1000000000000 .%
b0 -%
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bx (%
b0 '%
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0%%
b0 $%
b0 #%
bx "%
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bx ~$
bx }$
bx |$
bx {$
bx z$
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b0 p$
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bx \$
bx [$
bx Z$
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bx X$
bx W$
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b0 T$
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0Q$
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xM$
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xF$
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bx C$
bx000000000000 B$
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bx :$
x9$
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bx 7$
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b0 ~#
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b0 t#
0s#
b0 r#
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b0 m#
b100 l#
b0 k#
b0 j#
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b0 h#
b0 g#
b0 f#
b0 e#
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bx _#
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bx X#
bx W#
1V#
0U#
0T#
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bx P#
b0 O#
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b0 M#
b0 L#
b0 K#
bx J#
bx I#
1H#
0G#
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0A#
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bx 9#
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b1000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx y"
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$end
#1000
b100 6(
1;
#2000
0;
#3000
1;
#4000
0;
#5000
1;
#6000
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#7000
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0;
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b1 !#
b100 u"
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#15000
0s"
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#16000
0;
#17000
b100000000000000101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 y"
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 q"
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 {"
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 _#
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 0
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 +"
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 f"
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 o#
b101011000010110010011000000000000000000000001101101110000000000000000000000010011011100000000000000000000000010110111 0(
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