Test ordered binary lookup #4
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@ -4,7 +4,7 @@ Copyright - Yehowshua Immanuel
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## Current Features
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- pretty fast, parses 3.04 GB VCD file in ~54s on M1 Macbook Air with
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respect to 50s with GTKWave on the same device. FastWave currently
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respect to 30s with GTKWave on the same device. FastWave currently
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offers highly robust error handling which GTKWave doesn't have.
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I noticed that when running FastWave in the VsCode terminal as opposed
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@ -40,6 +40,7 @@ Here's a command to test on a malformed VCD:
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## Features
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- [ ] macro for getting line number when propagating errors
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- [ ] search for any unwraps or any direct vectors indexing
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- [ ] re-order all signal timelines as binary balanced trees with respect to timestamps
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- support multithreaded re-ordering
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- [ ] looks into making a macro for filename and linenumber later
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106
src/vcd/parse.rs
106
src/vcd/parse.rs
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@ -1,6 +1,6 @@
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use std::{fs::File};
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use std::collections::HashMap;
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use num::BigInt;
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use std::collections::HashMap;
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use std::fs::File;
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use super::*;
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@ -19,7 +19,44 @@ use scopes::*;
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mod events;
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use events::*;
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pub fn parse_vcd(file : File) -> Result<VCD, String> {
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use std::cmp::Ordering;
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fn compare_strs(a: &str, b: &str) -> Ordering {
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let last_idx = if a.len() > b.len() { a.len() } else { b.len() };
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// let last_idx += -1;
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Ordering::Less
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}
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fn ordered_binary_lookup(map: &Vec<(String, SignalIdx)>, key: &str) -> Result<SignalIdx, String> {
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let mut upper_idx = map.len() - 1;
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let mut lower_idx = 0usize;
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while lower_idx <= upper_idx {
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let mid_idx = lower_idx + ((upper_idx - lower_idx) / 2);
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let (str_val, signal_idx) = map.get(mid_idx).unwrap();
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let ordering = key.partial_cmp(str_val.as_str()).unwrap();
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match ordering {
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Ordering::Less => {
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upper_idx = mid_idx - 1;
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}
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Ordering::Equal => {
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return Ok(*signal_idx);
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}
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Ordering::Greater => {
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lower_idx = mid_idx + 1;
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}
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}
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}
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return Err(format!(
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"Error near {}:{}. Unable to find key: `{key}` in the map.",
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file!(),
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line!()
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));
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}
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pub fn parse_vcd(file: File) -> Result<VCD, String> {
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let mut word_gen = WordReader::new(file);
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let header = parse_metadata(&mut word_gen)?;
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@ -29,17 +66,48 @@ pub fn parse_vcd(file : File) -> Result<VCD, String> {
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let mut signal_map = std::collections::HashMap::new();
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// after we parse metadata, we form the VCD object
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let mut vcd = VCD{
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metadata : header,
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timeline : vec![],
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timeline_markers : vec![],
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all_signals : vec![],
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all_scopes : vec![],
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scope_roots : vec![],
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let mut vcd = VCD {
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metadata: header,
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timeline: vec![],
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timeline_markers: vec![],
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all_signals: vec![],
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all_scopes: vec![],
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scope_roots: vec![],
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};
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parse_scopes(&mut word_gen, &mut vcd, &mut signal_map)?;
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parse_events(&mut word_gen, &mut vcd, &mut signal_map)?;
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// the signal map should not contain any empty string
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for (k, v) in &signal_map {
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if k.len() == 0 {
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return Err(format!("Critical error near {}:{}. There should be no empty strings in vcd string -> SignalIdx hashmap.", file!(), line!()));
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}
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}
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// now that we've parsed all scopes and filled the hashmap
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// with signals, we convert hashmap to an ordered vector
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let mut signal_map1: Vec<(String, SignalIdx)> = signal_map
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.iter()
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.map(|(string, idx)| (string.clone(), idx.clone()))
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.collect();
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signal_map1.sort_by(|a: &(String, SignalIdx), b: &(String, SignalIdx)| {
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let a = &a.0;
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let b = &b.0;
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a.partial_cmp(&b).unwrap()
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});
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let now = std::time::Instant::now();
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for (k, v) in &signal_map1 {
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let signal_idx = ordered_binary_lookup(&signal_map1, k.as_str())?;
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assert!(*v == signal_idx);
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}
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let ordered_binary_search_elapsed = now.elapsed();
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println!(
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"ordered_binary_search_elapsed: {:.2?}",
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ordered_binary_search_elapsed
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);
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// parse_events(&mut wosrd_gen, &mut vcd, &mut signal_map)?;
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Ok(vcd)
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}
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@ -55,29 +123,18 @@ mod tests {
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// two loops
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// testing dates
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for file in test::GOOD_DATE_FILES {
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let metadata = parse_metadata(
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&mut WordReader::new(
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File::open(file)
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.unwrap()
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)
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);
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let metadata = parse_metadata(&mut WordReader::new(File::open(file).unwrap()));
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assert!(metadata.is_ok());
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assert!(metadata.unwrap().date.is_some());
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}
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for file in test::FILES {
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let metadata = parse_metadata(
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&mut WordReader::new(
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File::open(file)
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.unwrap()
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)
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);
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let metadata = parse_metadata(&mut WordReader::new(File::open(file).unwrap()));
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assert!(metadata.is_ok());
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let (scalar, _timescale) = metadata.unwrap().timescale;
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assert!(scalar.is_some());
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}
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}
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#[test]
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@ -94,6 +151,5 @@ mod tests {
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// assert!(vcd.is_ok());
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}
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}
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}
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134
src/vcd/types.rs
134
src/vcd/types.rs
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@ -4,18 +4,27 @@ use chrono::prelude::*;
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pub(super) struct Version(pub String);
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#[derive(Debug)]
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pub(super) enum Timescale {Fs, Ps, Ns, Us, Ms, S, Unit}
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pub(super) enum Timescale {
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Fs,
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Ps,
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Ns,
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Us,
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Ms,
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S,
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Unit,
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}
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#[derive(Debug)]
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pub(super) struct Metadata {
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pub(super) date : Option<DateTime<Utc>>,
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pub(super) version : Option<Version>,
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pub(super) timescale : (Option<u32>, Timescale)}
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pub(super) date: Option<DateTime<Utc>>,
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pub(super) version: Option<Version>,
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pub(super) timescale: (Option<u32>, Timescale),
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}
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#[derive(Debug, Copy, Clone)]
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pub(super) struct ScopeIdx(pub(super) usize);
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#[derive(Debug, Copy, Clone)]
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#[derive(Debug, Copy, Clone, PartialEq)]
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pub(super) struct SignalIdx(pub(super) usize);
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#[derive(Debug, Copy, Clone)]
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@ -25,63 +34,71 @@ pub(super) struct TimelineIdx(pub(super) u32);
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pub struct StartIdx(pub(super) u32);
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#[derive(Debug)]
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pub(super) enum SigType {Integer, Parameter, Real, Reg, Str, Wire, Tri1, Time}
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pub(super) enum SigType {
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Integer,
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Parameter,
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Real,
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Reg,
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Str,
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Wire,
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Tri1,
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Time,
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}
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#[derive(Debug)]
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pub(super) enum Signal{
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Data{
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name : String,
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sig_type : SigType,
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// I've seen a 0 bit signal parameter in a xilinx
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// simulation before that gets assigned 1 bit values.
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// I consider this to be bad behavior. We capture such
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// errors in the following type.
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signal_error : Option<String>,
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num_bits : Option<usize>,
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// TODO : may be able to remove self_idx
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self_idx : SignalIdx,
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// we could encounter a mix of pure values and strings
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// for the same signal timeline
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u8_timeline : Vec<u8>,
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u8_timeline_markers : Vec<TimelineIdx>,
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string_timeline : Vec<String>,
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string_timeline_markers : Vec<TimelineIdx>,
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scope_parent : ScopeIdx},
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Alias{
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name : String,
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signal_alias : SignalIdx}
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pub(super) enum Signal {
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Data {
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name: String,
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sig_type: SigType,
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// I've seen a 0 bit signal parameter in a xilinx
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// simulation before that gets assigned 1 bit values.
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// I consider this to be bad behavior. We capture such
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// errors in the following type.
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signal_error: Option<String>,
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num_bits: Option<usize>,
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// TODO : may be able to remove self_idx
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self_idx: SignalIdx,
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// we could encounter a mix of pure values and strings
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// for the same signal timeline
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u8_timeline: Vec<u8>,
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u8_timeline_markers: Vec<TimelineIdx>,
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string_timeline: Vec<String>,
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string_timeline_markers: Vec<TimelineIdx>,
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scope_parent: ScopeIdx,
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},
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Alias {
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name: String,
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signal_alias: SignalIdx,
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},
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}
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#[derive(Debug)]
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pub(super) struct Scope {
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pub(super) name : String,
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pub(super) name: String,
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pub(super) parent_idx : Option<ScopeIdx>,
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pub(super) self_idx : ScopeIdx,
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pub(super) child_signals : Vec<SignalIdx>,
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pub(super) child_scopes : Vec<ScopeIdx>}
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pub(super) parent_idx: Option<ScopeIdx>,
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pub(super) self_idx: ScopeIdx,
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pub(super) child_signals: Vec<SignalIdx>,
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pub(super) child_scopes: Vec<ScopeIdx>,
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}
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// TODO: document how timeline is represented
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#[derive(Debug)]
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pub struct VCD {
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pub(super) metadata : Metadata,
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pub timeline : Vec<u8>,
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pub timeline_markers : Vec<StartIdx>,
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pub(super) all_signals : Vec<Signal>,
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pub(super) all_scopes : Vec<Scope>,
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pub(super) scope_roots : Vec<ScopeIdx>}
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pub(super) metadata: Metadata,
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pub timeline: Vec<u8>,
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pub timeline_markers: Vec<StartIdx>,
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pub(super) all_signals: Vec<Signal>,
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pub(super) all_scopes: Vec<Scope>,
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pub(super) scope_roots: Vec<ScopeIdx>,
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}
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impl VCD {
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// TODO : make this a generic traversal function that applies specified
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// functions upon encountering scopes and signals
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fn print_scope_tree(
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&self,
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root_scope_idx : ScopeIdx,
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depth : usize)
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{
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let all_scopes = &self.all_scopes;
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fn print_scope_tree(&self, root_scope_idx: ScopeIdx, depth: usize) {
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let all_scopes = &self.all_scopes;
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let all_signals = &self.all_signals;
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let indent = " ".repeat(depth * 4);
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@ -94,17 +111,16 @@ impl VCD {
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for SignalIdx(ref signal_idx) in &root_scope.child_signals {
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let child_signal = &all_signals[*signal_idx];
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let name = match child_signal {
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Signal::Data{name, ..} => {name}
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Signal::Alias{name, ..} => {name}
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Signal::Data { name, .. } => name,
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Signal::Alias { name, .. } => name,
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};
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println!("{indent} - sig: {name}")
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}
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println!();
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for scope_idx in &root_scope.child_scopes {
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self.print_scope_tree(*scope_idx, depth+1);
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self.print_scope_tree(*scope_idx, depth + 1);
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}
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}
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pub fn print_scopes(&self) {
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@ -120,20 +136,20 @@ impl VCD {
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for signal in &self.all_signals {
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match signal {
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Signal::Alias {..} => {}
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Signal::Alias { .. } => {}
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Signal::Data {
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name,
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self_idx,
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u8_timeline,
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.. } => {
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if u8_timeline.len() > max_len {
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max_len = u8_timeline.len();
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let SignalIdx(idx_usize) = self_idx;
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idx = *idx_usize;
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signal_name = name.clone();
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}
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..
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} => {
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if u8_timeline.len() > max_len {
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max_len = u8_timeline.len();
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let SignalIdx(idx_usize) = self_idx;
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idx = *idx_usize;
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signal_name = name.clone();
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}
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}
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}
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}
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