Separate name from width #20

Merged
TheZoq2 merged 1 commit from name_width_separation into main 2023-10-23 13:28:03 +00:00
2 changed files with 25 additions and 0 deletions
Showing only changes of commit e7f2f661df - Show all commits

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@ -126,10 +126,12 @@ pub(super) fn parse_var<R: std::io::Read>(
// $var parameter 3 a IDLE $end
// ^^^^ - full_signal_name(can extend until $end)
let mut full_signal_name = Vec::<String>::new();
let mut size = None;
loop {
let (word, _) = next_word!(word_reader)?;
match word {
"$end" => break,
other if other.starts_with('[') => size = Some(other.to_string()),
_ => full_signal_name.push(word.to_string()),
}
}
@ -170,6 +172,7 @@ pub(super) fn parse_var<R: std::io::Read>(
.chain([full_signal_name])
.collect::<Vec<String>>(),
signal_type: var_type,
index: size,
signal_error: None,
num_bits,
num_bytes,

View file

@ -48,6 +48,11 @@ impl<'a> Signal<'a> {
signal_enum.name()
}
pub fn name_with_size(&self) -> String {
let Signal(signal_enum) = &self;
signal_enum.name_with_index()
}
pub fn path(&self) -> &[String] {
match self.0 {
SignalEnum::Data { path, .. } => path,
@ -135,6 +140,9 @@ pub(super) enum SignalEnum {
name: String,
path: Vec<String>,
signal_type: SignalType,
/// The optional [start:end] part of the signal name that is sometimes
/// added to signals
index: Option<String>,
/// I've seen a 0 bit signal parameter in a xilinx
/// simulation before that gets assigned 1 bit values.
/// I consider this to be bad behavior. We capture such
@ -218,6 +226,20 @@ impl SignalEnum {
}
.clone()
}
pub fn name_with_index(&self) -> String {
match self {
SignalEnum::Data {
name, index: None, ..
} => format!("{name}"),
SignalEnum::Data {
name,
index: Some(size),
..
} => format!("{name} {size}"),
SignalEnum::Alias { name, .. } => name.clone(),
}
}
}
// helper functions ultimately used by Signal's query functions later on