New parser #2
|
@ -8,4 +8,4 @@ edition = "2021"
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||||||
[dependencies]
|
[dependencies]
|
||||||
num = "0.4"
|
num = "0.4"
|
||||||
clap = { version = "3.1.8", features = ["derive"] }
|
clap = { version = "3.1.8", features = ["derive"] }
|
||||||
next-gen = "0.1.1"
|
chrono = "0.4"
|
35
README.md
35
README.md
|
@ -21,9 +21,44 @@ The first build of the program may take some time.
|
||||||
|
|
||||||
# TODO
|
# TODO
|
||||||
- [x] We need a way to merge lines.
|
- [x] We need a way to merge lines.
|
||||||
|
- [ ] Need to perform signal aliasing
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||||||
|
- use vec of enum {Sig, Alias}
|
||||||
|
- [ ] Should insert nodes in BFS order
|
||||||
- [ ] We need to start regression testing the parser over all files
|
- [ ] We need to start regression testing the parser over all files
|
||||||
- [ ] Take a look at GTKWave parser to compare effificiency.
|
- [ ] Take a look at GTKWave parser to compare effificiency.
|
||||||
- [ ] Send survey to community channel.
|
- [ ] Send survey to community channel.
|
||||||
|
|
||||||
### May 18
|
### May 18
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||||||
- [ ] move while loop into word yielding iterator
|
- [ ] move while loop into word yielding iterator
|
||||||
|
|
||||||
|
# Files
|
||||||
|
./test-vcd-files/aldec/SPI_Write.vcd
|
||||||
|
./test-vcd-files/ghdl/alu.vcd
|
||||||
|
./test-vcd-files/ghdl/idea.vcd
|
||||||
|
./test-vcd-files/ghdl/pcpu.vcd
|
||||||
|
./test-vcd-files/gtkwave-analyzer/perm_current.vcd
|
||||||
|
./test-vcd-files/icarus/CPU.vcd
|
||||||
|
./test-vcd-files/icarus/rv32_soc_TB.vcd
|
||||||
|
./test-vcd-files/icarus/test1.vcd
|
||||||
|
./test-vcd-files/model-sim/CPU_Design.msim.vcd
|
||||||
|
./test-vcd-files/model-sim/clkdiv2n_tb.vcd
|
||||||
|
./test-vcd-files/my-hdl/Simple_Memory.vcd
|
||||||
|
./test-vcd-files/my-hdl/sigmoid_tb.vcd
|
||||||
|
./test-vcd-files/my-hdl/top.vcd
|
||||||
|
./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd
|
||||||
|
./test-vcd-files/quartus/mipsHardware.vcd
|
||||||
|
./test-vcd-files/quartus/wave_registradores.vcd
|
||||||
|
./test-vcd-files/questa-sim/dump.vcd
|
||||||
|
./test-vcd-files/questa-sim/test.vcd
|
||||||
|
./test-vcd-files/riviera-pro/dump.vcd
|
||||||
|
./test-vcd-files/systemc/waveform.vcd
|
||||||
|
./test-vcd-files/treadle/GCD.vcd
|
||||||
|
./test-vcd-files/vcs/Apb_slave_uvm_new.vcd
|
||||||
|
./test-vcd-files/vcs/datapath_log.vcd
|
||||||
|
./test-vcd-files/vcs/processor.vcd
|
||||||
|
./test-vcd-files/verilator/swerv1.vcd
|
||||||
|
./test-vcd-files/verilator/vlt_dump.vcd
|
||||||
|
./test-vcd-files/vivado/iladata.vcd
|
||||||
|
./test-vcd-files/xilinx_isim/test.vcd
|
||||||
|
./test-vcd-files/xilinx_isim/test1.vcd
|
||||||
|
./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd
|
59
src/main.rs
59
src/main.rs
|
@ -2,7 +2,8 @@ use std::io::prelude::*;
|
||||||
use std::io;
|
use std::io;
|
||||||
use std::fs::File;
|
use std::fs::File;
|
||||||
use std::collections::BTreeMap;
|
use std::collections::BTreeMap;
|
||||||
use ::next_gen::prelude::*;
|
use chrono::prelude::*;
|
||||||
|
use std::rc::Rc;
|
||||||
|
|
||||||
use num::*;
|
use num::*;
|
||||||
use clap::Parser;
|
use clap::Parser;
|
||||||
|
@ -14,16 +15,53 @@ struct Cli {
|
||||||
path: std::path::PathBuf,
|
path: std::path::PathBuf,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// TODO: implement any timescales greater than a second
|
||||||
|
enum Timescale {ps, ns, us, ms, s}
|
||||||
|
|
||||||
|
struct Metadata {
|
||||||
|
date : DateTime<FixedOffset>,
|
||||||
|
version : String,
|
||||||
|
timescale : Timescale
|
||||||
|
}
|
||||||
|
|
||||||
struct Signal {
|
struct Signal {
|
||||||
name : String,
|
name : String,
|
||||||
timeline : BTreeMap<BigInt, BigInt>,
|
timeline : BTreeMap<BigInt, BigInt>,
|
||||||
children_arena: Vec<usize>,
|
children_arena: Vec<usize>,
|
||||||
parent_index : usize
|
parent_index : usize
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
struct SignalAlias {
|
||||||
|
name : String,
|
||||||
|
signal_alias : Rc<Signal>
|
||||||
|
}
|
||||||
|
|
||||||
|
enum SignalGeneric{
|
||||||
|
Signal(Signal),
|
||||||
|
SignalAlias(SignalAlias),
|
||||||
|
}
|
||||||
|
|
||||||
|
struct Scope {
|
||||||
|
name : String,
|
||||||
|
signals : Vec<SignalGeneric>,
|
||||||
|
scopes : Vec<Scope>,
|
||||||
|
}
|
||||||
|
|
||||||
|
struct VCD {
|
||||||
|
metadata : Metadata,
|
||||||
|
top_scopes : Vec<Scope>
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#[generator(yield(&str))]
|
enum VCD_Parser_State {Date, Version, Timescale, SignalTree, Values}
|
||||||
fn yield_words(file : File) {
|
enum Date_Parser_State {Date, Day, Month, HHMMSS, Year}
|
||||||
|
|
||||||
|
fn parse_vcd(word: &str, mut state : VCD_Parser_State) {}
|
||||||
|
fn parse_date(word : &str, mut state : Date_Parser_State) {}
|
||||||
|
|
||||||
|
fn yield_word_and_apply(file : File, mut f : impl FnMut(&str)) {
|
||||||
let mut reader = io::BufReader::new(file);
|
let mut reader = io::BufReader::new(file);
|
||||||
|
|
||||||
let mut buffer = String::new();
|
let mut buffer = String::new();
|
||||||
|
@ -43,24 +81,23 @@ fn yield_words(file : File) {
|
||||||
let words = buffer.split_ascii_whitespace();
|
let words = buffer.split_ascii_whitespace();
|
||||||
|
|
||||||
for word in words {
|
for word in words {
|
||||||
yield_!(word);
|
f(word);
|
||||||
}
|
}
|
||||||
|
|
||||||
buffer.clear();
|
buffer.clear();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
fn main() -> std::io::Result<()> {
|
fn main() -> std::io::Result<()> {
|
||||||
let args = Cli::parse();
|
let args = Cli::parse();
|
||||||
|
|
||||||
let file = File::open(&args.path)?;
|
// let dt = Utc.datetime_from_str("Fri Nov 28 12:00:09 2014", "%a %b %e %T %Y");
|
||||||
let mut word_count = 0;
|
|
||||||
mk_gen!(let mut generator = yield_words(file));
|
|
||||||
|
|
||||||
for word in generator {
|
let file = File::open(&args.path)?;
|
||||||
word_count += 1;
|
let mut word_count = 0;
|
||||||
}
|
|
||||||
|
yield_word_and_apply(file, |word| {word_count += 1});
|
||||||
|
dbg!(word_count);
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue