New parser #2
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@ -33,6 +33,7 @@ You can run all the tests with ``cargo test``
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able to successfully parse all sample VCDs.
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- [ ] Change error messages to line and filenames. Go through all calls to ``format!``
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whilst also keep performance in mind.
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- [ ] Create compressed fungible numeric enums with good heuristic support.
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- [ ] Print out git commit or release number.
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- [ ] Should be able to load waveform whilst viewing it live.
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- could be quite challenging to implement for various reasons
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@ -16,9 +16,17 @@ struct Cli {
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fn main() -> std::io::Result<()> {
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let args = Cli::parse();
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use std::time::Instant;
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let now = Instant::now();
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let file = File::open(&args.path)?;
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let vcd = parse_vcd(file).unwrap();
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let elapsed = now.elapsed();
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println!("Elapsed: {:.2?}", elapsed);
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vcd.print_longest_signal();
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// println!("printing signal tree");
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// vcd.print_scopes();
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325
src/vcd/parse.rs
325
src/vcd/parse.rs
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@ -1,5 +1,6 @@
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use std::{fs::File};
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use std::collections::HashMap;
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use chrono::format::format;
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use num::BigInt;
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use num::bigint::ToBigInt;
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@ -17,8 +18,84 @@ use metadata::*;
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mod scopes;
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use scopes::*;
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use std::num::{IntErrorKind, ParseIntError};
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use function_name::named;
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/// Sometimes, variables can be listed outside of scopes.
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/// We call these floating vars.
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pub(super) fn parse_orphaned_vars<'a>(
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word_reader : &mut WordReader,
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vcd : &'a mut VCD,
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signal_map : &mut HashMap<String, Signal_Idx>
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) -> Result<(), String> {
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// create scope for unscoped signals if such a scope does not
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// yet exist
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let scope_name = "Orphaned Signals";
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// set default scope_idx to the count of existing scope as we
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// generally set scope.self_idx to the number of existing scopes
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// when that particular scope was inserted
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let mut scope_idx = Scope_Idx(vcd.all_scopes.len());
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// Override scope_idx if we find a scope named "Orphaned Signals"
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// already exists
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let mut scope_already_exists = false;
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for scope in &vcd.all_scopes {
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if scope.name == scope_name {
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scope_idx = scope.self_idx;
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scope_already_exists = true;
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break
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}
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}
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if !scope_already_exists {
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vcd.all_scopes.push(
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Scope {
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name: scope_name.to_string(),
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parent_idx: None,
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self_idx: scope_idx,
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child_signals: vec![],
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child_scopes: vec![]
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}
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);
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vcd.scope_roots.push(scope_idx);
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}
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// we can go ahead and parse the current var as we've already encountered
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// "$var" before now.
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parse_var(word_reader, scope_idx, vcd, signal_map)?;
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loop {
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let next_word = word_reader.next_word();
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// we shouldn't reach the end of the file here...
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if next_word.is_none() {
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let (f, l )= (file!(), line!());
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let msg = format!("Error near {f}:{l}.\
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Reached end of file without terminating parser");
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Err(msg)?;
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};
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let (word, cursor) = next_word.unwrap();
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match word {
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"$var" => {
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parse_var(word_reader, scope_idx, vcd, signal_map)?;
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}
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"$scope" => {break}
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_ => {
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let (f, l )= (file!(), line!());
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let msg = format!("Error near {f}:{l}.\
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Expected $scope or $var, found {word} at {cursor:?}");
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Err(msg)?;
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}
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};
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}
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Ok(())
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}
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#[named]
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fn parse_events<'a>(
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word_reader : &mut WordReader,
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@ -41,9 +118,142 @@ fn parse_events<'a>(
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"$" => {}
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"#" => {
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let value = &word[1..];
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let time_cursor = BigInt::parse_bytes(value.as_bytes(), 10).ok_or(
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format!("failed to parse {value} as BigInt at {cursor:?}").as_str())?;
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vcd.cursor = time_cursor;
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// we try to parse the timestamp into the Value unsigned
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// variant used to hold the previous timestamp. Doing this
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// may fail with PosOverflow, which we would store in parse_ok,
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// and later try to remedy with bigger unsigned variants of Value.
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let parse_ok =
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if let Value::u8(_) = vcd.cursor {
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let value = value.parse::<u8>();
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match value {
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Ok(value) => {
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vcd.cursor = Value::u8(value);
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Ok(())
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}
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Err(e) => Err(e)
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}
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}
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else if let Value::u16(_) = vcd.cursor {
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let value = value.parse::<u16>();
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match value {
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Ok(value) => {
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vcd.cursor = Value::u16(value);
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Ok(())
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}
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Err(e) => Err(e)
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}
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}
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else if let Value::u32(_) = vcd.cursor {
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let value = value.parse::<u32>();
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match value {
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Ok(value) => {
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vcd.cursor = Value::u32(value);
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Ok(())
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}
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Err(e) => Err(e)
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}
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}
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else if let Value::u64(_) = vcd.cursor {
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let value = value.parse::<u64>();
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match value {
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Ok(value) => {
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vcd.cursor = Value::u64(value);
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Ok(())
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}
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Err(e) => Err(e)
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}
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}
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else {
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let value = BigInt::parse_bytes(value.as_bytes(), 10).ok_or(
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format!("failed to parse {value} as BigInt at {cursor:?}").as_str())?;
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vcd.cursor = Value::BigInt(value);
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Ok(())
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};
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// If there was no parse error, we don't evaluate any more logic
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// in this match arm and simply continue to the next iteration of
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// the outer loop to evaluate the next word.
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if parse_ok.is_ok() {
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continue
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}
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// Try parsing value as u16 since there was a previous
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// PosOverflow error, and record if this parse attempt
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// was Ok or Err in parse_ok.
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let parse_ok =
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{
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let e = parse_ok.unwrap_err();
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// There could have been other parse errors...
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// Return Err below if there were.
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if e.kind() != &IntErrorKind::PosOverflow {
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Err(format!("{e:?}"))?;
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}
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match value.parse::<u16>() {
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Ok(value) => {
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vcd.cursor = Value::u16(value);
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Ok(())
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}
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Err(e) => Err(e)
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}
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};
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// If there was no parse error, we don't evaluate any more logic
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// in this match arm and simply continue to the next iteration of
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// the outer loop to evaluate the next word.
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if parse_ok.is_ok() {
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continue
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}
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// Try parsing value as u32 since there was a previous
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// PosOverflow error, and record if this parse attempt
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// was Ok or Err in parse_ok.
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let parse_ok =
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{
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let e = parse_ok.unwrap_err();
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// There could have been other parse errors...
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// Return Err below if there were.
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if e.kind() != &IntErrorKind::PosOverflow {
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Err(format!("{e:?}"))?;
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}
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match value.parse::<u32>() {
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Ok(value) => {
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vcd.cursor = Value::u32(value);
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Ok(())
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}
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Err(e) => Err(e)
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}
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};
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// If there was no parse error, we don't evaluate any more logic
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// in this match arm and simply continue to the next iteration of
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// the outer loop to evaluate the next word.
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if parse_ok.is_ok() {
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continue
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}
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// Try parsing value as u64 since there was a previous
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// PosOverflow error, and record if this parse attempt
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// was Ok or Err in parse_ok.
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let parse_ok =
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{
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let e = parse_ok.unwrap_err();
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// There could have been other parse errors...
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// Return Err below if there were.
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if e.kind() != &IntErrorKind::PosOverflow {
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Err(format!("{e:?}"))?;
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}
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match value.parse::<u64>() {
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Ok(value) => {
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vcd.cursor = Value::u64(value);
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Ok(())
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}
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Err(e) => Err(e)
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}
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};
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}
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"0" => {
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// lokup signal idx
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@ -68,12 +278,13 @@ fn parse_events<'a>(
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// after handling potential indirection, go ahead and update the timeline
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// of the signal signal_idx references
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let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
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let signal = vcd.all_signals.get_mut(0usize).unwrap();
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// let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
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match signal {
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Signal::Data {name, sig_type, num_bits,
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self_idx, timeline, scope_parent} => {
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let value = 0.to_bigint().unwrap();
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let pair = (TimeStamp(vcd.cursor.clone()), Sig_Value::Numeric(value));
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let pair = (vcd.cursor.clone(), Value::u8(0));
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timeline.push(pair);
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Ok(())
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}
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@ -86,47 +297,47 @@ fn parse_events<'a>(
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}
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}?;
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}
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"1" => {
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// lokup signal idx
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let hash = &word[1..].to_string();
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let Signal_Idx(ref signal_idx) = signal_map.get(hash).ok_or(
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format!("failed to lookup signal {hash} at {cursor:?}").as_str())?;
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// "1" => {
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// // lokup signal idx
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// let hash = &word[1..].to_string();
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// let Signal_Idx(ref signal_idx) = signal_map.get(hash).ok_or(
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// format!("failed to lookup signal {hash} at {cursor:?}").as_str())?;
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// account for fact that signal idx could be an alias, so there
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// could be one step of indirection
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let signal_idx =
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{
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let signal = vcd.all_signals.get(*signal_idx).unwrap();
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match signal {
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Signal::Data {..} => {signal_idx.clone()}
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Signal::Alias {name, signal_alias} => {
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let Signal_Idx(ref signal_idx) = signal_alias;
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signal_idx.clone()
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// // account for fact that signal idx could be an alias, so there
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// // could be one step of indirection
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// let signal_idx =
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// {
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// let signal = vcd.all_signals.get(*signal_idx).unwrap();
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// match signal {
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// Signal::Data {..} => {signal_idx.clone()}
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// Signal::Alias {name, signal_alias} => {
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// let Signal_Idx(ref signal_idx) = signal_alias;
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// signal_idx.clone()
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}
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}
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};
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// }
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// }
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// };
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// after handling potential indirection, go ahead and update the timeline
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// of the signal signal_idx references
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let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
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match signal {
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Signal::Data {name, sig_type, num_bits,
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self_idx, timeline, scope_parent} => {
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let value = 1.to_bigint().unwrap();
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let pair = (TimeStamp(vcd.cursor.clone()), Sig_Value::Numeric(value));
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timeline.push(pair);
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Ok(())
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}
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Signal::Alias {..} => {
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let (f, l )= (file!(), line!());
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let msg = format!(
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"Error near {f}:{l}, a signal alias should not point to a signal alias.\n\
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This error occurred while parsing vcd file at {cursor:?}");
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Err(msg)
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}
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}?;
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}
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// // after handling potential indirection, go ahead and update the timeline
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// // of the signal signal_idx references
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// let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
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// match signal {
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// Signal::Data {name, sig_type, num_bits,
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// self_idx, timeline, scope_parent} => {
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// let value = 1.to_bigint().unwrap();
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// let pair = (TimeStamp(vcd.cursor.clone()), Sig_Value::Numeric(value));
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// timeline.push(pair);
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// Ok(())
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// }
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// Signal::Alias {..} => {
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// let (f, l )= (file!(), line!());
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// let msg = format!(
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// "Error near {f}:{l}, a signal alias should not point to a signal alias.\n\
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// This error occurred while parsing vcd file at {cursor:?}");
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// Err(msg)
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// }
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// }?;
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// }
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_ => {}
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}
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}
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@ -139,17 +350,41 @@ pub fn parse_vcd(file : File) -> Result<VCD, String> {
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let header = parse_metadata(&mut word_gen)?;
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// later, we'll need to map parsed ascii symbols to their
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// respective signal indexes
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let mut signal_map = std::collections::HashMap::new();
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// after we parse metadata, we form VCD object
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let mut vcd = VCD{
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metadata : header,
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cursor : 0.to_bigint().unwrap(),
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cursor : Value::u8(0),
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all_signals: vec![],
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all_scopes : vec![],
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scope_roots: vec![],
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};
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parse_scopes(&mut word_gen, None, &mut vcd, &mut signal_map)?;
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// The last word parse_metadata saw determines how we proceed.
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// There may be some orphan vars we must parse first before
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// parsing scoped vars.
|
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let (f, l ) = (file!(), line!());
|
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let msg = format!("Error near {f}:{l}. Current word empty!");
|
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let (word, cursor) = word_gen.curr_word().expect(msg.as_str());
|
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match word {
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"$scope" => {
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parse_scopes(&mut word_gen, None, &mut vcd, &mut signal_map)
|
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}
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"$var" => {
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parse_orphaned_vars(&mut word_gen, &mut vcd, &mut signal_map)?;
|
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parse_scopes(&mut word_gen, None, &mut vcd, &mut signal_map)
|
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}
|
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_ => {
|
||||
let (f, l )= (file!(), line!());
|
||||
let msg = format!("Error near {f}:{l}.\
|
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Expected $scope or $var, found {word} at {cursor:?}");
|
||||
Err(msg)
|
||||
}
|
||||
|
||||
}?;
|
||||
parse_events(&mut word_gen, &mut vcd, &mut signal_map)?;
|
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dbg!(&vcd.cursor);
|
||||
|
||||
|
|
|
|||
|
|
@ -315,10 +315,10 @@ pub(super) fn parse_metadata(word_reader : &mut WordReader) -> Result<Metadata,
|
|||
metadata.timescale = timescale.unwrap();
|
||||
}
|
||||
}
|
||||
// in VCDs, the scope keyword indicates the end of the metadata section
|
||||
"scope" => {break}
|
||||
"var" => {break}
|
||||
// we keep searching for words until we've found one of the following
|
||||
// keywords, ["version", "timescale", "scope"]
|
||||
// keywords, ["version", "timescale", "scope", "var"]
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ pub(super) fn parse_var<'a>(
|
|||
// ^ - signal_alias
|
||||
let (word, cursor) = word_reader.next_word().ok_or(&err)?;
|
||||
let signal_alias = word.to_string();
|
||||
// dbg!(&signal_alias);
|
||||
|
||||
// $var parameter 3 a IDLE $end
|
||||
// ^^^^ - full_signal_name(can extend until $end)
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ use std::str;
|
|||
use std::io::prelude::*;
|
||||
use std::io;
|
||||
|
||||
#[derive(Debug)]
|
||||
#[derive(Debug, Clone)]
|
||||
pub(super) struct Line(pub(super) usize);
|
||||
#[derive(Debug)]
|
||||
#[derive(Debug, Clone)]
|
||||
pub(super) struct Word(pub(super) usize);
|
||||
#[derive(Debug)]
|
||||
#[derive(Debug, Clone)]
|
||||
pub(super) struct Cursor(pub(super) Line, pub(super) Word);
|
||||
|
||||
impl Cursor {
|
||||
|
|
@ -26,6 +26,7 @@ pub struct WordReader {
|
|||
buffers : Vec<String>,
|
||||
curr_line : usize,
|
||||
str_slices : VecDeque<(*const u8, usize, Cursor)>,
|
||||
curr_slice : Option<(*const u8, usize, Cursor)>,
|
||||
}
|
||||
|
||||
impl WordReader {
|
||||
|
|
@ -36,7 +37,8 @@ impl WordReader {
|
|||
EOF : false,
|
||||
buffers : vec![],
|
||||
curr_line : 0,
|
||||
str_slices : VecDeque::new()
|
||||
str_slices : VecDeque::new(),
|
||||
curr_slice : None
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -83,7 +85,22 @@ impl WordReader {
|
|||
unsafe {
|
||||
let (ptr, len, position) = self.str_slices.pop_front().unwrap();
|
||||
let slice = slice::from_raw_parts(ptr, len);
|
||||
self.curr_slice = Some((ptr, len, position.clone()));
|
||||
return Some((str::from_utf8(slice).unwrap(), position));
|
||||
};
|
||||
}
|
||||
|
||||
pub(super) fn curr_word(&mut self) -> Option<(&str, Cursor)> {
|
||||
match &self.curr_slice {
|
||||
Some(slice) => {
|
||||
unsafe {
|
||||
let (ptr, len, position) = slice.clone();
|
||||
let slice = slice::from_raw_parts(ptr, len);
|
||||
Some((str::from_utf8(slice).unwrap(), position))
|
||||
}
|
||||
|
||||
}
|
||||
None => {None}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
use core::time;
|
||||
use std::collections::{BTreeMap, HashMap};
|
||||
use chrono::prelude::*;
|
||||
use num::BigInt;
|
||||
|
|
@ -24,11 +25,26 @@ pub(super) struct Signal_Idx(pub(super) usize);
|
|||
pub(super) enum Sig_Type {Integer, Parameter, Real, Reg, Str, Wire, Tri1, Time}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub(super) struct TimeStamp(pub(super) BigInt);
|
||||
pub(super) enum TimeStamp {
|
||||
u8(u8),
|
||||
u16(u16),
|
||||
u32(u32),
|
||||
u64(u64),
|
||||
BigInt(BigInt),
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
pub(super) enum Value {
|
||||
u8(u8),
|
||||
u16(u16),
|
||||
u32(u32),
|
||||
u64(u64),
|
||||
BigInt(BigInt),
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub(super) enum Sig_Value {
|
||||
Numeric(BigInt),
|
||||
Numeric(u64),
|
||||
NonNumeric(String)}
|
||||
|
||||
#[derive(Debug)]
|
||||
|
|
@ -39,7 +55,7 @@ pub(super) enum Signal{
|
|||
num_bits : Option<usize>,
|
||||
// TODO : may be able to remove self_idx
|
||||
self_idx : Signal_Idx,
|
||||
timeline : Vec<(TimeStamp, Sig_Value)>,
|
||||
timeline : Vec<(Value, Value)>,
|
||||
scope_parent : Scope_Idx},
|
||||
Alias{
|
||||
name : String,
|
||||
|
|
@ -61,7 +77,7 @@ pub(super) struct Scope {
|
|||
#[derive(Debug)]
|
||||
pub struct VCD {
|
||||
pub(super) metadata : Metadata,
|
||||
pub (super) cursor : BigInt,
|
||||
pub (super) cursor : Value,
|
||||
pub(super) all_signals : Vec<Signal>,
|
||||
pub(super) all_scopes : Vec<Scope>,
|
||||
pub(super) scope_roots : Vec<Scope_Idx>}
|
||||
|
|
@ -107,4 +123,33 @@ impl VCD {
|
|||
self.print_scope_tree(*scope_root, 0);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn print_longest_signal(&self) {
|
||||
let mut idx = 0usize;
|
||||
let mut max_len = 0usize;
|
||||
let mut signal_name = String::new();
|
||||
|
||||
for signal in &self.all_signals {
|
||||
match signal {
|
||||
Signal::Alias {..} => {}
|
||||
Signal::Data {
|
||||
name,
|
||||
sig_type,
|
||||
num_bits,
|
||||
self_idx,
|
||||
timeline,
|
||||
scope_parent } => {
|
||||
if timeline.len() > max_len {
|
||||
max_len = timeline.len();
|
||||
let Signal_Idx(idx_usize) = self_idx;
|
||||
idx = *idx_usize;
|
||||
signal_name = name.clone();
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dbg!((idx, max_len, signal_name));
|
||||
}
|
||||
}
|
||||
|
|
@ -1,4 +1,17 @@
|
|||
Icarus,Verilator,GHDL,VCS,QuestaSim,ModelSim,Quartus,SystemC,Treadle,Aldec,Riviera-PRO,MyHDL,ncsim,xilinx_isim,vivado,GTKWave-Analyzer,Amaranth
|
||||
https://github.com/dpretet/vcd/blob/master/test1.vcd,https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd,https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd,https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd,https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd,https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd,https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd,https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd,https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd,https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd,https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd,https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd,https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd,https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd,https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd,https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd,Locally Simulated File
|
||||
https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd,https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd,https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd,https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd,https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd,https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd,,https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd,,,,https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd,,https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd,https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd,,
|
||||
https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd,,https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd,https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd,,,,,,,,https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd,,https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd,,,
|
||||
Icarus,https://github.com/dpretet/vcd/blob/master/test1.vcd,https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd,https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd
|
||||
Verilator,https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd,https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd,
|
||||
GHDL,https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd,https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd,https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd
|
||||
VCS,https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd,https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd,https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd
|
||||
QuestaSim,https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd,https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd,
|
||||
ModelSim,https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd,https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd,
|
||||
Quartus,https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd,,
|
||||
SystemC,https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd,https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd,
|
||||
Treadle,https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd,,
|
||||
Aldec,https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd,,
|
||||
Riviera-PRO,https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd,,
|
||||
MyHDL,https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd,https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd,https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd
|
||||
ncsim,https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd,,
|
||||
xilinx_isim,https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd,https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd,https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd
|
||||
vivado,https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd,https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd,
|
||||
GTKWave-Analyzer,https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd,,
|
||||
Amaranth,Locally Simulated File,,
|
||||
|
Loading…
Reference in a new issue