Error when reading VCDs with systemverilog keywords #34

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opened 2023-10-21 16:20:46 +00:00 by andreasWallner · 0 comments

andreasWallner commented

2023-10-21 16:20:46 +00:00

(Migrated from github.com)

If a VCD file contains SV keywords (e.g. logic) I get an error while parsing:

[ERROR] 
   0: Failed to parse VCD file: ../git/spinalStuff/simWorkspace/andreasWallner.la.Leb128CompressorTest/test.vcd
   1: Error near FastWaveBackend/src/vcd/parse/scopes.rs:75 found keyword `logic` but expected one of
[test.zip](https://github.com/ThePerfectComputer/FastWaveBackend/files/13061192/test.zip)
 ["event", "integer", "parameter", "real", "realtime", "reg", "string", "supply0", "supply1", "time", "tri", "triand", "trior", "trireg", "tri0", "tri1", "wand", "wire", "wor"] on Cursor(Line(25), Word(2))

The VCD file was generated through fst2vcd from an fst file.

Edit: I tried to attach to offending file, for some reason github didn't let me upload the zip file, here an excerpt that reproduced the issue:

$date
	Thu Oct 12 01:15:30 2023

$end
$version
	fstWriter
$end
$timescale
	1s
$end
$scope module TOP $end
$var wire 3 ! io_data $end
$var wire 1 " io_compressed_valid $end
$var wire 16 # io_compressed_payload_compressed $end
$var wire 1 $ io_run $end
$var wire 1 % clk $end
$var wire 1 & reset $end
$scope module LEB128Compressor_3_16 $end
$var wire 3 ! io_data $end
$var wire 1 " io_compressed_valid $end
$var wire 16 # io_compressed_payload_compressed $end
$var wire 1 $ io_run $end
$var wire 1 % clk $end
$var wire 1 & reset $end
$var logic 3 ' io_data_regNext $end
$var wire 1 ( dataChange $end
$var logic 11 ) counter $end
$var logic 1 * counterFlagBits $end
$var wire 1 + extractedFlagBits $end
$var wire 1 , nextCounterFlagBits $end
$var wire 1 - maxCount $end
$var wire 1 . when_analyzer_l180 $end
$var wire 1 / dataFlagBits $end
$var wire 2 0 cumulated $end
$var wire 3 1 flagBits $end
$var wire 14 2 outputData $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b00000000000001 2
b001 1
b00 0
1/
0.
0-
0,
0+
0*
b00000000000 )

If a VCD file contains SV keywords (e.g. `logic`) I get an error while parsing: ``` [ERROR] 0: Failed to parse VCD file: ../git/spinalStuff/simWorkspace/andreasWallner.la.Leb128CompressorTest/test.vcd 1: Error near FastWaveBackend/src/vcd/parse/scopes.rs:75 found keyword `logic` but expected one of [test.zip](https://github.com/ThePerfectComputer/FastWaveBackend/files/13061192/test.zip) ["event", "integer", "parameter", "real", "realtime", "reg", "string", "supply0", "supply1", "time", "tri", "triand", "trior", "trireg", "tri0", "tri1", "wand", "wire", "wor"] on Cursor(Line(25), Word(2)) ``` The VCD file was generated through `fst2vcd` from an fst file. Edit: I tried to attach to offending file, for some reason github didn't let me upload the zip file, here an excerpt that reproduced the issue: ``` $date Thu Oct 12 01:15:30 2023 $end $version fstWriter $end $timescale 1s $end $scope module TOP $end $var wire 3 ! io_data $end $var wire 1 " io_compressed_valid $end $var wire 16 # io_compressed_payload_compressed $end $var wire 1 $ io_run $end $var wire 1 % clk $end $var wire 1 & reset $end $scope module LEB128Compressor_3_16 $end $var wire 3 ! io_data $end $var wire 1 " io_compressed_valid $end $var wire 16 # io_compressed_payload_compressed $end $var wire 1 $ io_run $end $var wire 1 % clk $end $var wire 1 & reset $end $var logic 3 ' io_data_regNext $end $var wire 1 ( dataChange $end $var logic 11 ) counter $end $var logic 1 * counterFlagBits $end $var wire 1 + extractedFlagBits $end $var wire 1 , nextCounterFlagBits $end $var wire 1 - maxCount $end $var wire 1 . when_analyzer_l180 $end $var wire 1 / dataFlagBits $end $var wire 2 0 cumulated $end $var wire 3 1 flagBits $end $var wire 14 2 outputData $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000001 2 b001 1 b00 0 1/ 0. 0- 0, 0+ 0* b00000000000 ) ```