Keep index as part of signal name #12

Merged

oscargus merged 1 commit from keepindex into main

2023-09-26 11:03:10 +00:00

oscargus commented

2023-09-13 11:25:36 +00:00

(Migrated from github.com)

Related to #9

I realize that the current behavior is a design choice, but probably it is better to leave it to the viewer to decide if this should be included or not.

Related to #9 I realize that the current behavior is a design choice, but probably it is better to leave it to the viewer to decide if this should be included or not.

TheZoq2 (Migrated from github.com) approved these changes 2023-09-19 13:03:32 +00:00

TheZoq2 (Migrated from github.com) left a comment

I realize that the current behavior is a design choice, but probably it is better to leave it to the viewer to decide if this should be included or not.

Agreed, for Surfer I think we should add a config to select if you want [] there or not, but striping it, especially when #9 is a problem is not ideal

> I realize that the current behavior is a design choice, but probably it is better to leave it to the viewer to decide if this should be included or not. Agreed, for Surfer I think we should add a config to select if you want [] there or not, but striping it, especially when #9 is a problem is not ideal

src/vcd/parse/scopes.rs

TheZoq2 (Migrated from github.com) commented

2023-09-19 13:02:30 +00:00

Is this correct? Verilog "raw" identifiers are supported and there may be a way to have spaces in those names. Might be better to insert spaces instead of mangling such (admittedly rare names)

Is this correct? Verilog "raw" identifiers are supported and there *may* be a way to have spaces in those names. Might be better to insert spaces instead of mangling such (admittedly rare names)