small update

README.md

@@ -1,4 +1,4 @@
-Copyright - Yehowshua Immanuel
+Copyright(2023) - Yehowshua Immanuel
 
 # Vision
 Imagine being able to visualize a CPU pipeline diagram by merely loading a simulation waveform dump, sprinkling in a bit of code, and dragging and dropping some diagram blocks into the visualizer. This project aims to offer such an experience.
@@ -6,10 +6,7 @@ Imagine being able to visualize a CPU pipeline diagram by merely loading a simul
 Since this project is written in Rust, it should also be able to run in the browser via web-assembly.
 
 # Status
-I hope to work on this more actively again soon.
+As of January 2024, work on the Fastwave Backend is stalled. It has been a fun journey watching Fastwave enable the first iterations of the [surfer waveform viewer](https://surfer-project.org). Now surfer uses an even better backend called [Wellen](https://github.com/ekiwi/wellen?tab=readme-ov-file). Go check it out! I hear it's really good. Perhaps I will soon archive the Fastwave Backend.
-
-The Zoq is is working on an excellent frontend call the Surfer. Check it out 
-[here](https://gitlab.com/surfer-project/surfer)!
 
 Browser demo: https://app.surfer-project.org/
 

examples/vcd.rs

@@ -73,7 +73,7 @@ fn main() -> std::io::Result<()> {
     let timestamps = vec![31499_000u32, 31500_000u32, 57760_000u32];
     for timestamp in timestamps {
         let time = num::BigUint::from(timestamp);
-        let val = state_signal.query_val_on_tmln(&time, &vcd).unwrap();
+        let val = state_signal.query_string_val_on_tmln(&time, &vcd).unwrap();
         println!("Signal `{name}` has value `{val}` at time `{time}`");
     }
 

src/lib.rs

@@ -5,7 +5,7 @@
 
 mod vcd;
 pub use vcd::parse::parse_vcd;
-pub use vcd::signal::{Signal, SignalErrors, SignalType, SignalValue};
+pub use vcd::signal::{Signal, SignalType, SignalValue, SignalErrors};
 pub use vcd::types::{Metadata, Timescale, Version};
 pub use vcd::types::{ScopeIdx, SignalIdx, VCD};
 

src/vcd/parse/scopes.rs

@@ -42,16 +42,6 @@ pub(super) fn parse_var<R: std::io::Read>(
         "wand",
         "wire",
         "wor",
-        "int",
-        "int_s",
-        "shortint",
-        "int_l",
-        "longint",
-        "char",
-        "byte",
-        "logic",
-        "bit",
-        "shortreal",
     ];
 
     // $var parameter 3 a IDLE $end
@@ -76,15 +66,6 @@ pub(super) fn parse_var<R: std::io::Read>(
         "wand" => Ok(SignalType::WAnd),
         "wire" => Ok(SignalType::Wire),
         "wor" => Ok(SignalType::WOr),
-        "int" => Ok(SignalType::SVInt),
-        "int_s" => Ok(SignalType::SVShortInt),
-        "shortint" => Ok(SignalType::SVShortInt),
-        "int_l" => Ok(SignalType::SVLongInt),
-        "longint" => Ok(SignalType::SVLongInt),
-        "logic" => Ok(SignalType::SVLogic),
-        "shortreal" => Ok(SignalType::SVShortReal),
-        "byte" => Ok(SignalType::SVChar),
-        "char" => Ok(SignalType::SVChar),
         _ => {
             let err = format!(
                 "Error near {}:{} \
@@ -103,7 +84,23 @@ pub(super) fn parse_var<R: std::io::Read>(
 
     // $var parameter 3 a IDLE $end
     //                ^ - num_bits
-    let num_bits = {
+    let num_bits = match var_type {
+        SignalType::Event
+        | SignalType::Integer
+        | SignalType::Parameter
+        | SignalType::Reg
+        | SignalType::Supply0
+        | SignalType::Supply1
+        | SignalType::Tri
+        | SignalType::TriAnd
+        | SignalType::TriOr
+        | SignalType::TriReg
+        | SignalType::Tri0
+        | SignalType::Tri1
+        | SignalType::Time
+        | SignalType::WAnd
+        | SignalType::Wire
+        | SignalType::WOr => {
             let num_bits = word
                 .parse::<usize>()
                 .unwrap_or_else(|_| panic!("{}", parse_err));
@@ -116,6 +113,9 @@ pub(super) fn parse_var<R: std::io::Read>(
                 )
             })?;
             Some(num_bits)
+        }
+        // for strings, reals, and realtimes we don't really care what the number of bits is
+        _ => None,
     };
 
     // $var parameter 3 a IDLE $end

src/vcd/signal.rs

@@ -1,5 +1,3 @@
-use std::fmt;
-
 // Copyright (C) 2022 Yehowshua Immanuel
 // This program is distributed under both the GPLV3 license
 // and the YEHOWSHUA license, both of which can be found at
@@ -34,13 +32,6 @@ pub enum SignalType {
     WAnd,
     Wire,
     WOr,
-    SVLogic,
-    SVInt,
-    SVShortInt,
-    SVLongInt,
-    SVChar,
-    SVBit,
-    SVShortReal,
 }
 
 #[derive(Debug, PartialEq)]
@@ -49,26 +40,11 @@ pub enum SignalValue {
     String(String),
 }
 
-impl fmt::Display for SignalValue {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        match self {
-            SignalValue::BigUint(num) =>        { write!(f, "BigUnit: {num}") }
-            SignalValue::String(val) => {write!(f, "String: {val}")}
-        }
-    }
-}
-
 pub struct QueryResult<T> {
     pub current: Option<(TimeStamp, T)>,
     pub next: Option<TimeStamp>,
 }
 
-impl fmt::Display for QueryResult<SignalValue> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, "(current: {:?}, next: {:?})", self.current, self.next)
-    }
-}
-
 pub struct Signal<'a>(pub(super) &'a SignalEnum);
 
 impl<'a> Signal<'a> {
@@ -489,7 +465,7 @@ impl SignalEnum {
         if lsb_indxs_of_string_tmstmp_vals_on_tmln.is_empty() {
             return Ok(QueryResult {
                 current: None,
-                next: None,
+                next: None
             });
         }
 
@@ -634,7 +610,7 @@ impl SignalEnum {
         if lsb_indxs_of_num_tmstmp_vals_on_tmln.is_empty() {
             return Ok(QueryResult {
                 current: None,
-                next: None,
+                next: None
             });
         }
 

tests/files.rs

@@ -5,9 +5,8 @@
 
 // TODO: we should eventually be able to only test on just
 // the files const
-pub const FILES: [&str; 32] = [
+pub const FILES: [&str; 31] = [
     "./tests/vcd-files/aldec/SPI_Write.vcd",
-    "./tests/vcd-files/fst2vcd/logic.vcd",
     "./tests/vcd-files/ghdl/alu.vcd",
     "./tests/vcd-files/ghdl/idea.vcd",
     "./tests/vcd-files/ghdl/pcpu.vcd",