diff --git a/src/vcd/parse/scopes.rs b/src/vcd/parse/scopes.rs
index c60deda..6a0f28c 100644
--- a/src/vcd/parse/scopes.rs
+++ b/src/vcd/parse/scopes.rs
@@ -386,7 +386,7 @@ pub(super) fn parse_scopes<'a, R: std::io::Read>(
                 ident(word_reader, "$end")?;
                 break;
             }
-            "comment" => {
+            "$comment" => {
                 // although we don't store comments, we still need to advance the
                 // word_reader cursor to the end of the comment
                 loop {
diff --git a/tests/files.rs b/tests/files.rs
index f5d2ac3..7832a85 100644
--- a/tests/files.rs
+++ b/tests/files.rs
@@ -5,7 +5,7 @@
 
 // TODO: we should eventually be able to only test on just
 // the files const
-pub const FILES : [&str; 30] = [
+pub const FILES : [&str; 31] = [
     "./tests/vcd-files/aldec/SPI_Write.vcd",
     "./tests/vcd-files/ghdl/alu.vcd",
     "./tests/vcd-files/ghdl/idea.vcd",
@@ -36,7 +36,8 @@ pub const FILES : [&str; 30] = [
     "./tests/vcd-files/xilinx_isim/test.vcd",
     "./tests/vcd-files/xilinx_isim/test1.vcd",
     // TODO : add signal ignore list to handle bitwidth mismatches
-    "./tests/vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
+    "./tests/vcd-files/xilinx_isim/test2x2_regex22_string1.vcd",
+    "./tests/vcd-files/scope_with_comment.vcd",
 ];
 
 pub const GOOD_DATE_FILES : [&str; 24] = [
@@ -73,4 +74,4 @@ pub const BAD_DATE_FILES : [&str; 6] = [
     "./test-vcd-files/systemc/waveform.vcd",
     "./test-vcd-files/treadle/GCD.vcd",
     "./test-vcd-files/vivado/iladata.vcd",
-];
\ No newline at end of file
+];
diff --git a/tests/vcd-files/scope_with_comment.vcd b/tests/vcd-files/scope_with_comment.vcd
new file mode 100644
index 0000000..cf17910
--- /dev/null
+++ b/tests/vcd-files/scope_with_comment.vcd
@@ -0,0 +1,296 @@
+$date
+	Sat Dec 26 15:33:14 2020
+$end
+$version
+	ModelSim Version 10.5b
+$end
+$timescale
+	1ns
+$end
+
+$scope module clkdiv2n_tb $end
+$comment foo $end
+$var reg 1 ! clk $end
+$var reg 1 " reset $end
+$var wire 1 # clk_out $end
+
+$scope module t1 $end
+$var parameter 32 $ WIDTH $end
+$var parameter 32 % N $end
+$var wire 1 & clk $end
+$var wire 1 ' reset $end
+$var wire 1 # clk_out $end
+$var reg 3 ( r_reg [2:0] $end
+$var wire 1 ) r_nxt [2] $end
+$var wire 1 * r_nxt [1] $end
+$var wire 1 + r_nxt [0] $end
+$var reg 1 , clk_track $end
+$upscope $end
+$comment foo $end
+$upscope $end
+$comment foo $end
+$enddefinitions $end
+#0
+$comment foo $end
+$dumpvars
+0!
+x"
+bx (
+x,
+b11 $
+b110 %
+x#
+x+
+x*
+x)
+x'
+0&
+$end
+#5
+1"
+1'
+b0 (
+0,
+1+
+0*
+0)
+0#
+#10
+1!
+1&
+#15
+0"
+0'
+#20
+0!
+0&
+#30
+1!
+1&
+b1 (
+0+
+1*
+#40
+0!
+0&
+#50
+1!
+1&
+b10 (
+1+
+#60
+0!
+0&
+#70
+1!
+1&
+b11 (
+0+
+0*
+1)
+#80
+0!
+0&
+#90
+1!
+1&
+b100 (
+1+
+#100
+0!
+0&
+#110
+1!
+1&
+b101 (
+0+
+1*
+#120
+0!
+0&
+#130
+1!
+1&
+b0 (
+1,
+1+
+0*
+0)
+1#
+#140
+0!
+0&
+#150
+1!
+1&
+b1 (
+0+
+1*
+#160
+0!
+0&
+#170
+1!
+1&
+b10 (
+1+
+#180
+0!
+0&
+#190
+1!
+1&
+b11 (
+0+
+0*
+1)
+#200
+0!
+0&
+#210
+1!
+1&
+b100 (
+1+
+#220
+0!
+0&
+#230
+1!
+1&
+b101 (
+0+
+1*
+#240
+0!
+0&
+#250
+1!
+1&
+b0 (
+0,
+1+
+0*
+0)
+0#
+#260
+0!
+0&
+#270
+1!
+1&
+b1 (
+0+
+1*
+#280
+0!
+0&
+#290
+1!
+1&
+b10 (
+1+
+#300
+0!
+0&
+#310
+1!
+1&
+b11 (
+0+
+0*
+1)
+#320
+0!
+0&
+#330
+1!
+1&
+b100 (
+1+
+#340
+0!
+0&
+#350
+1!
+1&
+b101 (
+0+
+1*
+#360
+0!
+0&
+#370
+1!
+1&
+b0 (
+1,
+1+
+0*
+0)
+1#
+#380
+0!
+0&
+#390
+1!
+1&
+b1 (
+0+
+1*
+#400
+0!
+0&
+#410
+1!
+1&
+b10 (
+1+
+#420
+0!
+0&
+#430
+1!
+1&
+b11 (
+0+
+0*
+1)
+#440
+0!
+0&
+#450
+1!
+1&
+b100 (
+1+
+#460
+0!
+0&
+#470
+1!
+1&
+b101 (
+0+
+1*
+#480
+0!
+0&
+#490
+1!
+1&
+b0 (
+0,
+1+
+0*
+0)
+0#
+#500
+0!
+0&
+#510
+1!
+1&
+b1 (
+0+
+1*