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Merge pull request #2 from ThePerfectComputer/new_parser

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New parser
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ThePerfectComputer 2022-08-01 17:00:00 -04:00 committed by GitHub
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.gitignore vendored
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/target /target
Cargo.lock Cargo.lock
# Created by https://www.toptal.com/developers/gitignore/api/macos
# Edit at https://www.toptal.com/developers/gitignore?templates=macos
### macOS ###
# General
.DS_Store
.AppleDouble
.LSOverride
# Icon must end with two \r
Icon
# Thumbnails
._*
# Files that might appear in the root of a volume
.DocumentRevisions-V100
.fseventsd
.Spotlight-V100
.TemporaryItems
.Trashes
.VolumeIcon.icns
.com.apple.timemachine.donotpresent
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
### macOS Patch ###
# iCloud generated files
*.icloud
# End of https://www.toptal.com/developers/gitignore/api/macos

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Cargo.toml
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@ -8,3 +8,6 @@ edition = "2021"
[dependencies] [dependencies]
num = "0.4" num = "0.4"
clap = { version = "3.1.8", features = ["derive"] } clap = { version = "3.1.8", features = ["derive"] }
chrono = "0.4"
function_name = "0.3.0"
itertools = "0.10.3"

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This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<https://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<https://www.gnu.org/licenses/why-not-lgpl.html>.

65
README.md
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@ -1,43 +1,48 @@
# The Beginnings of a high-performance, low memory footprint VCD Viewer in Rust for massive multi-GB waveforms Copyright - Yehowshua Immanuel
## Features # A High performance, VCD Parser written in Rust
- very fast
- loads 200MB of VCD waveform per second on an 8 core 2017 desktop CPU with NVMe storage ## Current Features
- consumes roughly between 10 - 50MB of memory per GB of waveform - pretty fast, parses 3.04 GB VCD file in ~67s on M1 Macbook Air with
- elegant/pretty UI respect to 50s with GTKWave on the same device. FastWave currently
- can be easily ported to work in browser via webassembly offers highly robust error handling which GTKWave doesn't have.
- allows high-performance custom Rust plugins to manipulate and
generate new waveforms live
# Current Limitations
Unable to handle VCD files that have signals with more than
2^32 - 1 = 4,294,967,295 deltas/changes.
## Running ## Running
Make sure you have a test vcd file to get you started. You can grab This repository comes with several smaller VCD files emitted from
a large VCD file from various EDA tools. If you want a larger VCD file, grab one from
[here](https://drive.google.com/file/d/1pfm2qo2l8fGTHHJ8TLrg1vSGaV_TUbp2/view?usp=sharing). [here](https://drive.google.com/file/d/1pfm2qo2l8fGTHHJ8TLrg1vSGaV_TUbp2/view?usp=sharing).
The first build of the program may take some time. The first build of the program may take some time.
``cargo run --release -- path/to/vcd/file`` ``cargo run --release test-vcd-files/aldec/SPI_Write.vcd``
## TODO You can run all the tests with ``cargo test``
- [x] Test positions with seeking
- [x] vcd should be argument
- [x] structure to store stream position against timestamp as string
- [x] structure to store stream position against timestamp as BigInt
### April 14 # TODO
- [ ] store timestamps to struct
- [ ] Get file loading status
- [ ] Get all signal scopes
### April 15 ## Features
- [ ] Re-factor to support hooks in the initial file ingest - [ ] move parse_orphaned_vars to scopes.rs
- [ ] Modularize - [ ] Print out git commit or release number.
- [ ] Should be able to load waveform whilst viewing it live.
- could be quite challenging to implement for various reasons
- [ ] Take a look at GTKWave parser to compare efficiency.
- [ ] re-order all signal timelines as binary balanced trees with respect to timestamps
- support multithreaded re-ordering
### April 15 ## Repairs
- [ ] Build tree per signal. - [ ] make a custom date parser for possibly up to 18 different versions(that is, for each possible tool).
- [ ] Each signal also comes with a value change buffer to - [ ] Consolidate error messages and add cursors throughout.
avoid frequent disk readouts. - [ ] Fix warnings especially usage and restriction warnings once I'm
able to successfully parse all sample VCDs.
# VCD Spec Questions ## Code Consistency
- [ ] I'm pretty sure that only one statement per line is allowed. - [ ] Change error messages to line and filenames. Go through all calls to ``format!`` whilst also keeping performance in mind.
## Marketing
- [ ] Send survey to community channel.

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src/main.rs
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use std::io::prelude::*; use std::{fs::File};
use std::io;
use std::fs::File;
use num::*;
use clap::Parser; use clap::Parser;
pub mod test;
use test::*;
pub mod vcd;
use vcd::parse_vcd;
use std::mem::size_of_val;
#[derive(Parser)] #[derive(Parser)]
struct Cli { struct Cli {
/// The path to the file to read /// The path to the file to read
#[clap(parse(from_os_str))] #[clap(parse(from_os_str))]
path: std::path::PathBuf, path: std::path::PathBuf}
}
struct Timestamp{
file_offset: u64,
timestamp: BigInt
}
fn main() -> std::io::Result<()> { fn main() -> std::io::Result<()> {
let args = Cli::parse(); let args = Cli::parse();
let file = File::open(&args.path)?; use std::time::Instant;
let mut reader = io::BufReader::new(file); let now = Instant::now();
let mut buffer = String::new(); let file = File::open(&args.path)?;
let mut timestamp_offsets = Vec::new(); let vcd = parse_vcd(file).unwrap();
let mut timestamps = Vec::new();
while { let elapsed = now.elapsed();
let bytes_read = reader.read_line(&mut buffer).unwrap(); println!("Elapsed: {:.2?}", elapsed);
bytes_read > 0
} {
if &buffer[0..1] == "#" {
let pos = reader.stream_position().unwrap();
timestamp_offsets.push(pos);
let timestamp = { vcd.print_longest_signal();
let len = buffer.len(); dbg!(size_of_val(&*vcd.timeline));
let str_val = &buffer[1..(len - 1)].as_bytes(); // unsafe {
BigInt::parse_bytes(str_val, 10).unwrap() // let sz = size_of_val(&*vcd.timeline);
}; // }
timestamps.push(timestamp);
}
buffer.clear()
}
let index = 4; // println!("printing signal tree");
let timestamp_offset = timestamp_offsets.get(index).unwrap(); // vcd.print_scopes();
let timestamp = timestamps.get(index).unwrap();
dbg!((timestamp_offset, timestamp));
// seek to where we found the first timestamp and read
// out the next line
reader.seek(io::SeekFrom::Start(*timestamp_offset));
reader.read_line(&mut buffer);
dbg!(buffer);
Ok(()) Ok(())
} }

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mod files;
pub use files::*;

71
src/test/files.rs Normal file
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// TODO: we should eventually be able to only test on just
// the files const
pub const files : [&str; 30] = [
"./test-vcd-files/aldec/SPI_Write.vcd",
"./test-vcd-files/ghdl/alu.vcd",
"./test-vcd-files/ghdl/idea.vcd",
"./test-vcd-files/ghdl/pcpu.vcd",
"./test-vcd-files/gtkwave-analyzer/perm_current.vcd",
"./test-vcd-files/icarus/CPU.vcd",
"./test-vcd-files/icarus/rv32_soc_TB.vcd",
"./test-vcd-files/icarus/test1.vcd",
"./test-vcd-files/model-sim/CPU_Design.msim.vcd",
"./test-vcd-files/model-sim/clkdiv2n_tb.vcd",
"./test-vcd-files/my-hdl/Simple_Memory.vcd",
"./test-vcd-files/my-hdl/sigmoid_tb.vcd",
"./test-vcd-files/my-hdl/top.vcd",
"./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
"./test-vcd-files/quartus/mipsHardware.vcd",
"./test-vcd-files/quartus/wave_registradores.vcd",
"./test-vcd-files/questa-sim/dump.vcd",
"./test-vcd-files/questa-sim/test.vcd",
"./test-vcd-files/riviera-pro/dump.vcd",
"./test-vcd-files/systemc/waveform.vcd",
"./test-vcd-files/treadle/GCD.vcd",
"./test-vcd-files/vcs/Apb_slave_uvm_new.vcd",
"./test-vcd-files/vcs/datapath_log.vcd",
"./test-vcd-files/vcs/processor.vcd",
"./test-vcd-files/verilator/swerv1.vcd",
"./test-vcd-files/verilator/vlt_dump.vcd",
"./test-vcd-files/vivado/iladata.vcd",
"./test-vcd-files/xilinx_isim/test.vcd",
"./test-vcd-files/xilinx_isim/test1.vcd",
// TODO : add signal ignore list to handle bitwidth mismatches
"./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
];
pub const good_date_files : [&str; 24] = [
"./test-vcd-files/aldec/SPI_Write.vcd",
"./test-vcd-files/ghdl/alu.vcd",
"./test-vcd-files/ghdl/idea.vcd",
"./test-vcd-files/ghdl/pcpu.vcd",
"./test-vcd-files/gtkwave-analyzer/perm_current.vcd",
"./test-vcd-files/icarus/CPU.vcd",
"./test-vcd-files/icarus/rv32_soc_TB.vcd",
"./test-vcd-files/icarus/test1.vcd",
"./test-vcd-files/model-sim/CPU_Design.msim.vcd",
"./test-vcd-files/model-sim/clkdiv2n_tb.vcd",
"./test-vcd-files/my-hdl/Simple_Memory.vcd",
"./test-vcd-files/my-hdl/sigmoid_tb.vcd",
"./test-vcd-files/my-hdl/top.vcd",
"./test-vcd-files/questa-sim/dump.vcd",
"./test-vcd-files/questa-sim/test.vcd",
"./test-vcd-files/riviera-pro/dump.vcd",
"./test-vcd-files/vcs/Apb_slave_uvm_new.vcd",
"./test-vcd-files/vcs/datapath_log.vcd",
"./test-vcd-files/vcs/processor.vcd",
"./test-vcd-files/verilator/swerv1.vcd",
"./test-vcd-files/verilator/vlt_dump.vcd",
"./test-vcd-files/xilinx_isim/test.vcd",
"./test-vcd-files/xilinx_isim/test1.vcd",
"./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
];
pub const bad_date_files : [&str; 6] = [
"./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
"./test-vcd-files/quartus/mipsHardware.vcd",
"./test-vcd-files/quartus/wave_registradores.vcd",
"./test-vcd-files/systemc/waveform.vcd",
"./test-vcd-files/treadle/GCD.vcd",
"./test-vcd-files/vivado/iladata.vcd",
];

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mod reader;
pub use reader::*;
mod types;
pub use types::*;
mod parse;
pub use parse::*;

668
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use std::{fs::File};
use std::collections::HashMap;
use num::BigInt;
use super::*;
mod combinator_atoms;
use combinator_atoms::*;
mod types;
use types::*;
mod metadata;
use metadata::*;
mod scopes;
use scopes::*;
use std::num::{IntErrorKind, ParseIntError};
use function_name::named;
#[derive(Debug)]
enum BinaryParserErrTypes {x_value, z_value, u_value, other_value(char), too_long}
fn binary_str_to_vec_u8(binary_str : &str) -> Result<Vec<u8>, BinaryParserErrTypes> {
let mut vec_u8 : Vec<u8> = Vec::new();
let mut binary_str_as_bytes = binary_str.as_bytes();
let mut tail_idx = binary_str_as_bytes.len();
// clamp head if provided binary str is less than 8 long
let mut head_idx =
if tail_idx >= 8
{binary_str_as_bytes.len() - 8}
else
{0};
while {tail_idx > 0} {
let curr_b_val = &binary_str_as_bytes[head_idx..tail_idx];
let val_u8 = base2_str_to_byte(curr_b_val)?;
vec_u8.push(val_u8);
if head_idx < 8 {
head_idx = 0
}
else {
head_idx = head_idx - 8;
}
if tail_idx < 8 {
tail_idx = 0
}
else {
tail_idx = tail_idx - 8;
}
}
Ok(vec_u8)
}
fn base2_str_to_byte(word : &[u8]) -> Result<u8, BinaryParserErrTypes> {
let mut val = 0u8;
// shouldn't have more than 8 chars in str
let len = word.len();
if len > 8 {
let (f, l )= (file!(), line!());
let err = format!(
"Error near {f}:{l}. Base2 string has length {len} > 8.");
return Err(BinaryParserErrTypes::too_long)
}
let bit_lut = [
0b0000_0001u8,
0b0000_0010u8,
0b0000_0100u8,
0b0000_1000u8,
0b0001_0000u8,
0b0010_0000u8,
0b0100_0000u8,
0b1000_0000u8
];
for (idx, chr) in word.iter().rev().enumerate() {
match chr {
b'1' => {val = bit_lut[idx] | val}
b'0' => {}
b'x' | b'X' => {return Err(BinaryParserErrTypes::x_value)}
b'z' | b'Z' => {return Err(BinaryParserErrTypes::z_value)}
b'u' | b'U' => {return Err(BinaryParserErrTypes::u_value)}
_ => {return Err(BinaryParserErrTypes::other_value(*chr as char))}
}
}
Ok(val)
}
/// Sometimes, variables can be listed outside of scopes.
/// We call these floating vars.
pub(super) fn parse_orphaned_vars<'a>(
word_reader : &mut WordReader,
vcd : &'a mut VCD,
signal_map : &mut HashMap<String, Signal_Idx>
) -> Result<(), String> {
// create scope for unscoped signals if such a scope does not
// yet exist
let scope_name = "Orphaned Signals";
// set default scope_idx to the count of existing scope as we
// generally set scope.self_idx to the number of existing scopes
// when that particular scope was inserted
let mut scope_idx = Scope_Idx(vcd.all_scopes.len());
// Override scope_idx if we find a scope named "Orphaned Signals"
// already exists
let mut scope_already_exists = false;
for scope in &vcd.all_scopes {
if scope.name == scope_name {
scope_idx = scope.self_idx;
scope_already_exists = true;
break
}
}
if !scope_already_exists {
vcd.all_scopes.push(
Scope {
name: scope_name.to_string(),
parent_idx: None,
self_idx: scope_idx,
child_signals: vec![],
child_scopes: vec![]
}
);
vcd.scope_roots.push(scope_idx);
}
// we can go ahead and parse the current var as we've already encountered
// "$var" before now.
parse_var(word_reader, scope_idx, vcd, signal_map)?;
loop {
let next_word = word_reader.next_word();
// we shouldn't reach the end of the file here...
if next_word.is_none() {
let (f, l )= (file!(), line!());
let msg = format!("Error near {f}:{l}.\
Reached end of file without terminating parser");
Err(msg)?;
};
let (word, cursor) = next_word.unwrap();
match word {
"$var" => {
parse_var(word_reader, scope_idx, vcd, signal_map)?;
}
"$scope" => {break}
_ => {
let (f, l )= (file!(), line!());
let msg = format!("Error near {f}:{l}.\
Expected $scope or $var, found {word} at {cursor:?}");
Err(msg)?;
}
};
}
Ok(())
}
#[named]
fn parse_events<'a>(
word_reader : &mut WordReader,
vcd : &'a mut VCD,
signal_map : &mut HashMap<String, Signal_Idx>
) -> Result<(), String> {
loop {
let next_word = word_reader.next_word();
// if we've reached the end of the file, then there is obviously
// nothing left to do...
if next_word.is_none() {break};
let (word, cursor) = next_word.unwrap();
let Cursor(Line(_), Word(word_in_line_idx)) = cursor;
// we only want to match on the first word in a line
if word_in_line_idx != 1 {continue}
match &word[0..1] {
"$" => {}
"#" => {
let value = &word[1..];
let (f, l )= (file!(), line!());
let value = BigInt::parse_bytes(value.as_bytes(), 10).ok_or(
format!("Error near {f}:{l}. Failed to parse {value} as BigInt at {cursor:?}").as_str())?;
let (_, mut value) = value.to_bytes_le();
// TODO : u32 helps with less memory, but should ideally likely be
// configurable.
let (f, l )= (file!(), line!());
let start_idx = u32::try_from(vcd.timeline.len()).map_err(
|e| format!("Error near {f}:{l}. Failed to convert from usize to u32."))?;
vcd.timeline_markers.push(StartIdx(start_idx));
vcd.timeline.append(&mut value);
}
// handle the case of an n bit signal whose value must be parsed
"b" => {
let binary_value = &word[1..];
let observed_num_bits = binary_value.len();
let (f, l )= (file!(), line!());
let mut value_u8 : Vec<u8> = Vec::new();
let mut value_string = String::new();
let mut store_as_string = false;
// If we encounter x or z in a value, we can recover from
// the error and store the value as a string.
// Or else, we we propagate up other errors.
match binary_str_to_vec_u8(binary_value) {
Ok(result) => {value_u8 = result;}
Err(BinaryParserErrTypes::x_value |
BinaryParserErrTypes::z_value |
BinaryParserErrTypes::u_value
) =>
{
store_as_string = true;
value_string = binary_value.to_string();
}
Err(e) => {
let (f, l )= (file!(), line!());
Err(e).map_err(
|e| format!("Error near {f}:{l}. Error {e:?} at {cursor:?}."))?;
}
}
// this word should be the signal alias
let (word, cursor) = word_reader.next_word().unwrap();
// lookup signal idx
let (f, l )= (file!(), line!());
let Signal_Idx(ref signal_idx) = signal_map.get(word).ok_or(
format!("Error near {f}:{l}. Failed to lookup signal {word} at {cursor:?}"))?;
// account for fact that signal idx could be an alias, so there
// could be one step of indirection
let signal_idx =
{
let signal = vcd.all_signals.get(*signal_idx).unwrap();
match signal {
Signal::Data {..} => {*signal_idx}
Signal::Alias {name, signal_alias} => {
let Signal_Idx(ref signal_idx) = signal_alias;
signal_idx.clone()
}
}
};
// after handling potential indirection, go ahead and update the timeline
// of the signal signal_idx references
let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
match signal {
Signal::Data {name, sig_type, ref mut signal_error, num_bits,
self_idx, u8_timeline, u8_timeline_markers, string_timeline,
string_timeline_markers, ..} => {
if signal_error.is_some() {continue;}
// Get the observed number of bits for the value parsed earlier
// and verify that it is not greater than the numbits declared
// when the signal was declared.
// Also account for the error case of a bitwidth of `None`
match num_bits {
Some(ref num_bits) => {
if *num_bits > observed_num_bits {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
of sig_type {sig_type:?} is expected to be `1` not \
`{num_bits}`. \
This error occurred while parsing the vcd file at \
{cursor:?}");
*signal_error = Some(msg);
continue;
}
}
None => {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
must be specified for a signal of type {sig_type:?}. \
This error occurred while parsing the vcd file at \
{cursor:?}");
Err(msg)?;
}
};
let (f, l )= (file!(), line!());
let timeline_idx = u32::try_from(vcd.timeline.len()).map_err(
|e| format!("Error near {f}:{l}. Failed to convert from usize to u32."))?;
let timeline_idx = TimelineIdx(timeline_idx);
if store_as_string {
string_timeline_markers.push(timeline_idx);
string_timeline.push(value_string);
Ok(())
}
else {
u8_timeline_markers.push(timeline_idx);
u8_timeline.append(&mut value_u8);
Ok(())
}
}
Signal::Alias {..} => {
let (f, l )= (file!(), line!());
let msg = format!(
"Error near {f}:{l}, a signal alias should not point to a signal alias.\n\
This error occurred while parsing vcd file at {cursor:?}");
Err(msg)
}
}?;
}
// handle the case of a one bit signal whose value is set to `0`
"0" => {
// lookup signal idx
let hash = &word[1..];
let (f, l )= (file!(), line!());
let Signal_Idx(ref signal_idx) = signal_map.get(hash).ok_or(
format!("Error near {f}:{l}. Failed to lookup signal {hash} at {cursor:?}"))?;
// account for fact that signal idx could be an alias, so there
// could be one step of indirection
let signal_idx =
{
let signal = vcd.all_signals.get(*signal_idx).unwrap();
match signal {
Signal::Data {..} => {*signal_idx}
Signal::Alias {name, signal_alias} => {
let Signal_Idx(ref signal_idx) = signal_alias;
signal_idx.clone()
}
}
};
// after handling potential indirection, go ahead and update the timeline
// of the signal signal_idx references
let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
match signal {
Signal::Data {name, sig_type, ref mut signal_error, num_bits,
self_idx, u8_timeline, u8_timeline_markers, ..} => {
// if this is a bad signal, go ahead and skip it
if signal_error.is_some() {continue;}
// Get bitwidth and verify that it is 1.
// Also account for the error case of a bitwidth of `None`
match num_bits {
Some(ref num_bits) => {
if *num_bits != 1 {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
of sig_type {sig_type:?} is expected to be `1` not \
`{num_bits}`. \
This error occurred while parsing the vcd file at \
{cursor:?}");
*signal_error = Some(msg);
continue;
}
}
None => {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
must be specified for a signal of type {sig_type:?}. \
This error occurred while parsing the vcd file at \
{cursor:?}");
Err(msg)?;
}
};
let (f, l )= (file!(), line!());
let timeline_idx = u32::try_from(vcd.timeline.len()).map_err(
|e| format!("Error near {f}:{l}. Failed to convert from usize to u32."))?;
let timeline_idx = TimelineIdx(timeline_idx);
u8_timeline_markers.push(timeline_idx);
u8_timeline.push(0u8);
Ok(())
}
Signal::Alias {..} => {
let (f, l )= (file!(), line!());
let msg = format!(
"Error near {f}:{l}, a signal alias should not point to a signal alias.\n\
This error occurred while parsing vcd file at {cursor:?}");
Err(msg)
}
}?;
}
// other one bit cases
"x" | "X" | "z" | "Z" | "u" | "U" => {
let val = word.to_string();
// lokup signal idx
let hash = &word[1..];
let (f, l )= (file!(), line!());
let Signal_Idx(ref signal_idx) = signal_map.get(hash).ok_or(
format!("Error near {f}:{l}. Failed to lookup signal {hash} at {cursor:?}"))?;
// account for fact that signal idx could be an alias, so there
// could be one step of indirection
let signal_idx =
{
let signal = vcd.all_signals.get(*signal_idx).unwrap();
match signal {
Signal::Data {..} => {*signal_idx}
Signal::Alias {name, signal_alias} => {
let Signal_Idx(ref signal_idx) = signal_alias;
signal_idx.clone()
}
}
};
// after handling potential indirection, go ahead and update the timeline
// of the signal signal_idx references
let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
match signal {
Signal::Data {name, sig_type, ref mut signal_error, num_bits,
self_idx, u8_timeline, u8_timeline_markers, string_timeline,
string_timeline_markers, ..} => {
// if this is a bad signal, go ahead and skip it
if signal_error.is_some() {continue;}
// Get bitwidth and verify that it is 1.
// Also account for the error case of a bitwidth of `None`
match num_bits {
Some(ref num_bits) => {
if *num_bits != 1 {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
of sig_type {sig_type:?} is expected to be `1` not \
`{num_bits}`. \
This error occurred while parsing the vcd file at \
{cursor:?}");
*signal_error = Some(msg);
continue;
}
}
None => {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
must be specified for a signal of type {sig_type:?}. \
This error occurred while parsing the vcd file at \
{cursor:?}");
Err(msg)?;
}
};
let (f, l )= (file!(), line!());
let timeline_idx = u32::try_from(vcd.timeline.len()).map_err(
|e| format!("Error near {f}:{l}. Failed to convert from usize to u32."))?;
let timeline_idx = TimelineIdx(timeline_idx);
string_timeline_markers.push(timeline_idx);
string_timeline.push(val);
Ok(())
}
Signal::Alias {..} => {
let (f, l )= (file!(), line!());
let msg = format!(
"Error near {f}:{l}, a signal alias should not point to a signal alias.\n\
This error occurred while parsing vcd file at {cursor:?}");
Err(msg)
}
}?;
}
"1" => {
// lokup signal idx
let hash = &word[1..];
let (f, l )= (file!(), line!());
let Signal_Idx(ref signal_idx) = signal_map.get(hash).ok_or(
format!("Error near {f}:{l}. Failed to lookup signal {hash} at {cursor:?}"))?;
// account for fact that signal idx could be an alias, so there
// could be one step of indirection
let signal_idx =
{
let signal = vcd.all_signals.get(*signal_idx).unwrap();
match signal {
Signal::Data {..} => {*signal_idx}
Signal::Alias {name, signal_alias} => {
let Signal_Idx(ref signal_idx) = signal_alias;
signal_idx.clone()
}
}
};
// after handling potential indirection, go ahead and update the timeline
// of the signal signal_idx references
let signal = vcd.all_signals.get_mut(signal_idx).unwrap();
match signal {
Signal::Data {name, sig_type, ref mut signal_error, num_bits,
self_idx, u8_timeline, u8_timeline_markers, scope_parent, ..} => {
// if this is a bad signal, go ahead and skip it
if signal_error.is_some() {continue;}
// Get bitwidth and verify that it is 1.
// Also account for the error case of a bitwidth of `None`
match num_bits {
Some(ref num_bits) => {
if *num_bits != 1 {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
of sig_type {sig_type:?} is expected to be `1` not \
`{num_bits}`. \
This error occurred while parsing the vcd file at \
{cursor:?}");
*signal_error = Some(msg);
continue;
}
}
None => {
let (f, l) = (file!(), line!());
let msg = format!("\
Error near {f}:{l}. The bitwidth for signal {name} \
must be specified for a signal of type {sig_type:?}. \
This error occurred while parsing the vcd file at \
{cursor:?}");
Err(msg)?;
}
};
let (f, l )= (file!(), line!());
let timeline_idx = u32::try_from(vcd.timeline.len()).map_err(
|e| format!("Error near {f}:{l}. Failed to convert from usize to u32."))?;
let timeline_idx = TimelineIdx(timeline_idx);
u8_timeline_markers.push(timeline_idx);
u8_timeline.push(1u8);
Ok(())
}
Signal::Alias {..} => {
let (f, l )= (file!(), line!());
let msg = format!(
"Error near {f}:{l}, a signal alias should not point to a signal alias.\n\
This error occurred while parsing vcd file at {cursor:?}");
Err(msg)
}
}?;
}
_ => {}
}
}
Ok(())
}
pub fn parse_vcd(file : File) -> Result<VCD, String> {
let mut word_gen = WordReader::new(file);
let header = parse_metadata(&mut word_gen)?;
// later, we'll need to map parsed ascii symbols to their
// respective signal indexes
let mut signal_map = std::collections::HashMap::new();
// after we parse metadata, we form VCD object
let mut vcd = VCD{
metadata : header,
timeline : vec![],
timeline_markers : vec![],
all_signals : vec![],
all_scopes : vec![],
scope_roots : vec![],
};
// The last word parse_metadata saw determines how we proceed.
// There may be some orphan vars we must parse first before
// parsing scoped vars.
let (f, l ) = (file!(), line!());
let msg = format!("Error near {f}:{l}. Current word empty!");
let (word, cursor) = word_gen.curr_word().ok_or(msg)?;
match word {
"$scope" => {
parse_scopes(&mut word_gen, None, &mut vcd, &mut signal_map)
}
"$var" => {
parse_orphaned_vars(&mut word_gen, &mut vcd, &mut signal_map)?;
parse_scopes(&mut word_gen, None, &mut vcd, &mut signal_map)
}
_ => {
let (f, l )= (file!(), line!());
let msg = format!("Error near {f}:{l}.\
Expected $scope or $var, found {word} at {cursor:?}");
Err(msg)
}
}?;
parse_events(&mut word_gen, &mut vcd, &mut signal_map)?;
Ok(vcd)
}
#[cfg(test)]
mod tests {
use super::*;
use crate::test;
use std::fs::File;
#[test]
fn headers() {
// TODO: eventually, once all dates pass, merge the following
// two loops
// testing dates
for file in test::good_date_files {
let metadata = parse_metadata(
&mut WordReader::new(
File::open(file)
.unwrap()
)
);
assert!(metadata.is_ok());
assert!(metadata.unwrap().date.is_some());
}
for file in test::files {
let metadata = parse_metadata(
&mut WordReader::new(
File::open(file)
.unwrap()
)
);
assert!(metadata.is_ok());
let (scalar, timescale) = metadata.unwrap().timescale;
assert!(scalar.is_some());
}
}
#[test]
fn scopes() {
// see if we can parse all signal trees successfully
for file_name in test::files {
let file = File::open(file_name).unwrap();
let vcd = parse_vcd(file);
if !vcd.is_ok() {
dbg!(file_name);
vcd.unwrap();
}
// assert!(vcd.is_ok());
}
}
}

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use super::types::ParseResult;
use super::reader::WordReader;
pub(super) fn digit(chr : u8) -> bool {
let zero = b'0' as u8;
let nine = b'9' as u8;
let between_zero_and_nine = (chr >= zero) && (nine >= chr);
return between_zero_and_nine
}
pub(super) fn take_until<'a>(word : &'a str, pattern : u8) -> ParseResult<'a> {
let mut new_start = 0;
for chr in word.as_bytes() {
if (*chr == pattern) {
break
}
else {
new_start += 1;
}
}
return
ParseResult{
matched : &word[0..new_start],
residual : &word[new_start..]
};
}
// TODO: if I end up using simulator specific date parsers, ``take_until`` may
// suffice rendering this function obselete, at which point I should delete it.
pub(super) fn truncate_last_chr_when<'a>(word : &'a str, cond : fn(u8) -> bool) -> &'a str {
let last_chr = word.as_bytes().last().unwrap();
let mut new_end_index = word.len();
if cond(*last_chr) {
new_end_index -= 1;
}
return &word[0..new_end_index]
}
pub(super) fn take_while<'a>(word : &'a str, cond : fn(u8) -> bool) -> ParseResult<'a> {
let mut new_start = 0;
for chr in word.as_bytes() {
if (cond(*chr)) {
new_start += 1;
}
else {
break
}
}
return
ParseResult{
matched : &word[0..new_start],
residual : &word[new_start..]
};
}
pub(super) fn tag<'a>(word : &'a str, pattern : &'a str) -> ParseResult<'a> {
let lhs = word.as_bytes().iter();
let rhs = pattern.as_bytes();
let iter = lhs.zip(rhs);
let mut new_start = 0;
let mut res = true;
for (c_lhs, c_rhs) in iter {
res = res && (c_lhs == c_rhs);
if !res {break}
new_start += 1;
}
return
ParseResult{
matched : &word[0..new_start],
residual : &word[new_start..]
};
}
pub(super) fn ident(
word_reader : &mut WordReader,
keyword : &str,
) -> Result<(), String> {
// let keyword = "module";
let err : Result<(), String> = Err(format!("reached end of file without parser leaving ident"));
let word = word_reader.next_word();
let (word, cursor) = word.ok_or(err).unwrap();
if word == keyword {
return Ok(())
}
else {
let err = format!("found keyword `{word}` but expected `{keyword}` on {cursor:?}");
return Err(err)
}
}

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use chrono::prelude::*;
use itertools::Itertools;
use std::fs::File;
use function_name::named;
use super::*;
#[named]
pub(super) fn parse_date(
word_and_ctx1 : (&str, &Cursor),
word_and_ctx2 : (&str, &Cursor),
word_and_ctx3 : (&str, &Cursor),
word_and_ctx4 : (&str, &Cursor),
word_and_ctx5 : (&str, &Cursor),
) -> Result<DateTime<Utc>, String> {
let day = {
// check for another word in the file
let (word, cursor) = word_and_ctx1;
let days = ["Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"];
if !days.contains(&word) {
let msg = format!("reached end of file without parser leaving {}\n", function_name!());
let msg2 = format!("{word} is not a valid weekday : expected one of {days:?}\n");
let msg3 = format!("failure location: {cursor:?}");
return Err(format!("{}{}{}", msg, msg2, msg3))
}
word.to_string()
};
let month = {
// check for another word in the file
let (word, cursor) = word_and_ctx2;
let months = [
"Jan", "Feb", "Mar", "Apr",
"May", "Jun", "Jul", "Aug",
"Sept", "Oct", "Nov", "Dec",
];
if !months.contains(&word) {
let msg = format!("reached end of file without parser leaving {}\n", function_name!());
let msg2 = format!("{word} is not a valid month : expected one of {months:?}\n");
let msg3 = format!("failure location: {cursor:?}");
return Err(format!("{}{}{}", msg, msg2, msg3))
}
word.to_string()
};
let date = {
// check for another word in the file
let (word, cursor) = word_and_ctx3;
let date : u8 = match word.to_string().parse() {
Ok(date) => date,
Err(_) => {return Err("".to_string())}
};
if date > 31 {
let msg = format!("reached end of file without parser leaving {}\n", function_name!());
let msg2 = format!("{word} is not a valid date : must be between 0 and 31\n");
let msg3 = format!("failure location: {cursor:?}");
return Err(format!("{}{}{}", msg, msg2, msg3))
}
date.to_string()
};
let (hh, mm, ss) = {
// get hour
let (word, cursor) = word_and_ctx4;
let res = take_until(word, b':');
res.assert_match()?;
let hh : u8 = res.matched.to_string()
.parse()
.map_err(|_| "failed to parse".to_string())?;
if hh > 23 {
let msg = format!("reached end of file without parser leaving {}\n", function_name!());
let msg2 = format!("{hh} is not a valid hour : must be between 0 and 23\n");
let msg3 = format!("failure location: {cursor:?}");
return Err(format!("{}{}{}", msg, msg2, msg3))
}
// get minute
let word = &res.residual[1..]; // chop off colon which is at index 0
let res = take_until(word, b':');
res.assert_match()?;
let mm : u8 = res.matched.to_string()
.parse()
.map_err(|_| "failed to parse".to_string())?;
if mm > 60 {
let msg = format!("reached end of file without parser leaving {}\n", function_name!());
let msg2 = format!("{mm} is not a valid minute : must be between 0 and 60\n");
let msg3 = format!("failure location: {cursor:?}");
return Err(format!("{}{}{}", msg, msg2, msg3))
}
// get second
// let ss : u8 = remainder.to_string().parse().unwrap();
res.assert_residual()?;
let residual = &res.residual[1..]; // chop of colon which is at index 0
let ss : u8 = residual.to_string()
.parse()
.map_err(|_| "failed to parse".to_string())?;
if ss > 60 {
let msg = format!("reached end of file without parser leaving {}\n", function_name!());
let msg2 = format!("{ss} is not a valid second : must be between 0 and 60\n");
let msg3 = format!("failure location: {cursor:?}");
return Err(format!("{}{}{}", msg, msg2, msg3))
}
(hh.to_string(), mm.to_string(), ss.to_string())
};
let year = {
// check for another word in the file
let (word, cursor) = word_and_ctx5;
word.to_string()
};
// unfortunately, the minutes, seconds, and hour could occur in an
// unexpected order
let full_date = format!("{day} {month} {date} {hh}:{mm}:{ss} {year}");
let full_date = Utc.datetime_from_str(full_date.as_str(), "%a %b %e %T %Y");
if full_date.is_ok() {
return Ok(full_date.unwrap())
}
Err("failed to parse date".to_string())
}
#[named]
pub(super) fn parse_version(word_reader : &mut WordReader) -> Result<Version, String> {
let mut version = String::new();
loop {
let word = word_reader.next_word();
// if there isn't another word left in the file, then we exit
if word.is_none() {
return Err(format!("reached end of file without parser leaving {}", function_name!()))
}
let (word, cursor) = word.unwrap();
if word == "$end" {
// truncate trailing whitespace
let version = version[0..(version.len() - 1)].to_string();
return Ok(Version(version))
}
else {
version.push_str(word);
version.push_str(" ");
}
}
}
#[named]
pub(super) fn parse_timescale(word_reader : &mut WordReader) -> Result<(Option<u32>, Timescale), String> {
let err_msg = format!("failed in {}", function_name!());
// we might see `scalarunit $end` or `scalar unit $end`
// first get timescale
let (word, cursor) = word_reader.next_word().ok_or(&err_msg)?;
let word = word.to_string();
let ParseResult{matched, residual} = take_while(word.as_str(), digit);
let scalar = matched;
let scalar : u32 = scalar.to_string().parse()
.map_err(|_| &err_msg)?;
let timescale = {
if residual == "" {
let (word, cursor) = word_reader.next_word().ok_or(&err_msg)?;
let unit = match word {
"fs" => {Ok(Timescale::fs)}
"ps" => {Ok(Timescale::ps)}
"ns" => {Ok(Timescale::ns)}
"us" => {Ok(Timescale::us)}
"ms" => {Ok(Timescale::ms)}
"s" => {Ok(Timescale::s)}
_ => {Err(err_msg.to_string())}
}.unwrap();
(Some(scalar), unit)
}
else {
let unit = match residual {
"ps" => {Ok(Timescale::ps)}
"ns" => {Ok(Timescale::ns)}
"us" => {Ok(Timescale::us)}
"ms" => {Ok(Timescale::ms)}
"s" => {Ok(Timescale::s)}
_ => {Err(err_msg.to_string())}
}.unwrap();
(Some(scalar), unit)
}
};
// then check for the `$end` keyword
let (end, cursor) = word_reader.next_word().ok_or(&err_msg)?;
tag(end, "$end").assert_match()?;
return Ok(timescale);
Err("".to_string())
}
#[named]
pub(super) fn parse_metadata(word_reader : &mut WordReader) -> Result<Metadata, String> {
let err_msg = format!("reached end of file without parser leaving {}", function_name!());
let mut metadata = Metadata {
date : None,
version : None,
timescale : (None, Timescale::unit)
};
loop {
// check for another word in the file
let (word, cursor) = word_reader.next_word().ok_or(&err_msg)?;
let ParseResult{matched, residual} = tag(word, "$");
match matched {
// we hope that this word stars with a `$`
"$" => {
match residual {
"date" => {
let err_msg = format!("reached end of file without parser leaving {}", function_name!());
// a date is typically composed of the 5 following words which can
// occur in any order:
// {Day, Month, Date(number in month), hh:mm:ss, year}.
// Thus, we must lookahead read the 5 next words, and try our date
// parser on 5! = 120 permutations of the 5 words.
//
// It is also possible that within each permutation, the hours,
// minutes, and seconds could be in an unusual order, which means
// that we may search up to 6 different permutations oh hh::mm:ss,
// for an upper bound total of 720 permutations
//
// While looking ahead, if one of the 5 words in `$end`, we have to
// immediately stop trying to get more words.
let mut found_end = false;
let mut lookahead_5_words : Vec<(String, Cursor)> = Vec::new();
for word in 0..5 {
let (word, cursor) = word_reader.next_word().expect(err_msg.as_str());
let word = word.to_string();
match word.as_str() {
"$end" => {
found_end = true;
break;
}
_ => {
lookahead_5_words.push((word, cursor));
}
};
}
// we no longer attempt to parse date if we weren't able to lookahead 5
// words
if found_end {continue}
let permutations = lookahead_5_words
.iter()
.permutations(lookahead_5_words.len());
// go ahead and search for a match amongst permuted date text
for mut permutations in permutations {
let (w1, s1) = permutations.pop().unwrap();
let arg_1 = (&w1[..], s1);
let (w2, s2) = permutations.pop().unwrap();
let arg_2 = (&w2[..], s2);
let (w3, s3) = permutations.pop().unwrap();
let arg_3 = (&w3[..], s3);
let (w4, s4) = permutations.pop().unwrap();
let arg_4 = (&w4[..], s4);
let (w5, s5) = permutations.pop().unwrap();
let arg_5 = (&w5[..], s5);
let parsed_date = parse_date(arg_1, arg_2, arg_3, arg_4, arg_5);
// store date and exit loop if a match is found
if parsed_date.is_ok() {
metadata.date = Some(parsed_date.unwrap());
break
}
}
}
"version" => {
let version = parse_version(word_reader);
if version.is_ok() {
metadata.version = Some(version.unwrap());
}
}
"timescale" => {
let timescale = parse_timescale(word_reader);
if timescale.is_ok() {
metadata.timescale = timescale.unwrap();
}
}
"scope" => {break}
"var" => {break}
// we keep searching for words until we've found one of the following
// keywords, ["version", "timescale", "scope", "var"]
_ => {}
}
}
// if word does not start with `$`, then we keep looping
_ => {}
}
}
return Ok(metadata)
}

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//! part of the vcd parser that handles parsing the signal tree and
//! building the resulting signal tree
use function_name::named;
use super::*;
#[named]
pub(super) fn parse_var<'a>(
word_reader : &mut WordReader,
parent_scope_idx : Scope_Idx,
vcd : &'a mut VCD,
signal_map : &mut HashMap<String, Signal_Idx>
) -> Result<(), String> {
let err = format!("reached end of file without parser leaving {}", function_name!());
let (word, cursor) = word_reader.next_word().ok_or(&err)?;
let expected_types = ["integer", "parameter", "real", "reg", "string", "wire", "tri1", "time"];
// $var parameter 3 a IDLE $end
// ^^^^^^^^^ - var_type
let var_type = match word {
"integer" => {Ok(Sig_Type::Integer)}
"parameter" => {Ok(Sig_Type::Parameter)}
"real" => {Ok(Sig_Type::Real)}
"reg" => {Ok(Sig_Type::Reg)}
"string" => {Ok(Sig_Type::Str)}
"wire" => {Ok(Sig_Type::Wire)}
"tri1" => {Ok(Sig_Type::Tri1)}
"time" => {Ok(Sig_Type::Time)}
_ => {
let err = format!("found keyword `{word}` but expected one of {expected_types:?} on {cursor:?}");
Err(err)
}
}?;
let (word, cursor) = word_reader.next_word().ok_or(&err)?;
let parse_err = format!("failed to parse as usize on {cursor:?}");
// $var parameter 3 a IDLE $end
// ^ - no_bits
let no_bits = match var_type {
Sig_Type::Integer | Sig_Type::Parameter |
Sig_Type::Real | Sig_Type::Reg |
Sig_Type::Wire | Sig_Type::Tri1 |
Sig_Type::Time => {
let no_bits = word.parse::<usize>().expect(parse_err.as_str());
Some(no_bits)
}
// for strings, we don't really care what the number of bits is
_ => {None}
};
// $var parameter 3 a IDLE $end
// ^ - signal_alias
let (word, cursor) = word_reader.next_word().ok_or(&err)?;
let signal_alias = word.to_string();
// dbg!(&signal_alias);
// $var parameter 3 a IDLE $end
// ^^^^ - full_signal_name(can extend until $end)
let mut full_signal_name = Vec::<String>::new();
loop {
let (word, cursor) = word_reader.next_word().ok_or(&err)?;
match word {
"$end" => {break}
_ => {full_signal_name.push(word.to_string())}
}
}
let full_signal_name = full_signal_name.join(" ");
// Is the current variable an alias to a signal already encountered?
// if so, handle ref_signal_idx accordingly, if not, add signal to hash
// map
let (signal, signal_idx) = match signal_map.get(&signal_alias) {
Some(ref_signal_idx) => {
let signal_idx = Signal_Idx(vcd.all_signals.len());
let signal = Signal::Alias{
name: full_signal_name,
signal_alias: *ref_signal_idx};
(signal, signal_idx)
}
None => {
let signal_idx = Signal_Idx(vcd.all_signals.len());
signal_map.insert(signal_alias.to_string(), signal_idx);
let signal = Signal::Data{
name: full_signal_name,
sig_type: var_type,
signal_error: None,
num_bits: no_bits,
self_idx: signal_idx,
u8_timeline: vec![],
u8_timeline_markers: vec![],
string_timeline: vec![],
string_timeline_markers: vec![],
scope_parent: parent_scope_idx };
(signal, signal_idx)
}
};
vcd.all_signals.push(signal);
let Scope_Idx(parent_scope_idx_usize) = parent_scope_idx;
let parent_scope = vcd.all_scopes.get_mut(parent_scope_idx_usize).unwrap();
parent_scope.child_signals.push(signal_idx);
Ok(())
}
#[named]
pub(super) fn parse_signal_tree<'a>(
word_reader : &mut WordReader,
parent_scope_idx : Option<Scope_Idx>,
vcd : &'a mut VCD,
signal_map : &mut HashMap<String, Signal_Idx>
) -> Result<(), String> {
// $scope module reg_mag_i $end
// ^^^^^^ - module keyword
let err = format!("reached end of file without parser leaving {}", function_name!());
let (keyword, cursor) = word_reader.next_word().ok_or(&err)?;
let expected = ["module", "begin", "task", "function"];
if expected.contains(&keyword) {
Ok(())
} else {
let err = format!("found keyword `{keyword}` but expected one of `{expected:?}` on {cursor:?}");
Err(err)
}?;
// $scope module reg_mag_i $end
// ^^^^^^^^^ - scope name
let (scope_name, _) = word_reader.next_word().ok_or(&err)?;
let curr_scope_idx = Scope_Idx(vcd.all_scopes.len());
// register this scope as a child of the current parent scope
// if there is a parent scope, or else we register this scope as
// root scope
match parent_scope_idx {
Some(Scope_Idx(parent_scope_idx)) => {
let parent_scope = vcd.all_scopes.get_mut(parent_scope_idx).unwrap();
parent_scope.child_scopes.push(curr_scope_idx);
}
None => {
vcd.scope_roots.push(curr_scope_idx)
}
}
// add this scope to list of existing scopes
vcd.all_scopes.push(
Scope {
name: scope_name.to_string(),
parent_idx: parent_scope_idx,
self_idx: curr_scope_idx,
child_signals: vec![],
child_scopes: vec![]
}
);
// $scope module reg_mag_i $end
// ^^^^ - end keyword
ident(word_reader, "$end")?;
let err = format!("reached end of file without parser leaving {}", function_name!());
loop {
let (word, cursor) = word_reader.next_word().ok_or(&err)?;
let ParseResult{matched, residual} = tag(word, "$");
match matched {
// we hope that this word starts with a `$`
"$" => {
match residual {
"scope" => {
// recursive - parse inside of current scope tree
parse_signal_tree(word_reader, Some(curr_scope_idx), vcd, signal_map)?;
}
"var" => {
parse_var(word_reader, curr_scope_idx, vcd, signal_map)?;
}
"upscope" => {
ident(word_reader, "$end")?;
break
}
// we ignore comments
"comment" => {
loop {
if ident(word_reader, "$end").is_ok() {break}
}
}
_ => {
let err = format!("found keyword `{residual}` but expected `$scope`, `$var`, `$comment`, or `$upscope` on {cursor:?}");
return Err(err)
}
}
}
_ => {
let err = format!("found keyword `{matched}` but expected `$` on {cursor:?}");
return Err(err)
}
}
}
Ok(())
}
#[named]
pub(super) fn parse_scopes<'a>(
word_reader : &mut WordReader,
parent_scope_idx : Option<Scope_Idx>,
vcd : &'a mut VCD,
signal_map : &mut HashMap<String, Signal_Idx>
) -> Result<(), String> {
// we've already seen `$scope`, so here we just jump right in
parse_signal_tree(word_reader, None, vcd, signal_map)?;
let err = format!("reached end of file without parser leaving {}", function_name!());
let expected_keywords = ["$scope", "$enddefinitions"];
loop {
let (word, cursor) = word_reader.next_word().ok_or(&err)?;
match word {
"$scope" => {
parse_signal_tree(word_reader, None, vcd, signal_map)?;
}
"$enddefinitions" => {
ident(word_reader, "$end")?;
break
}
// we ignore comments
"comment" => {
loop {
if ident(word_reader, "$end").is_ok() {break}
}
}
_ => {
let err = format!("found keyword `{word}` but expected oneof `{expected_keywords:?}` on {cursor:?}");
return Err(err)
}
}
}
Ok(())
}

25
src/vcd/parse/types.rs Normal file
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@ -0,0 +1,25 @@
#[derive(Debug)]
pub(super) struct ParseResult<'a> {
pub(super) matched : &'a str,
pub(super) residual : &'a str}
impl<'a> ParseResult<'a> {
pub(super) fn assert_match(& self) -> Result<&str, String> {
if self.matched == "" {
return Err("no match".to_string())
}
else {
return Ok(self.matched)
}
}
pub(super) fn assert_residual(& self) -> Result<&str, String> {
if self.residual == "" {
return Err("no residual".to_string())
}
else {
return Ok(self.residual)
}
}
}

106
src/vcd/reader.rs Normal file
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@ -0,0 +1,106 @@
use std::fs::File;
use std::collections::VecDeque;
use std::slice;
use std::str;
use std::io::prelude::*;
use std::io;
#[derive(Debug, Clone)]
pub(super) struct Line(pub(super) usize);
#[derive(Debug, Clone)]
pub(super) struct Word(pub(super) usize);
#[derive(Debug, Clone)]
pub(super) struct Cursor(pub(super) Line, pub(super) Word);
impl Cursor {
pub(super) fn error(&self, word : &str) -> Result<(), String> {
let Cursor(Line(line_no), Word(word_no)) = self;
Err(format!("Error on word '{word}' {word_no} words into line {line_no}!"))
}
}
pub struct WordReader {
reader : io::BufReader<File>,
EOF : bool,
buffers : Vec<String>,
curr_line : usize,
str_slices : VecDeque<(*const u8, usize, Cursor)>,
curr_slice : Option<(*const u8, usize, Cursor)>,
}
impl WordReader {
pub(super) fn new(file : File) -> WordReader {
let mut reader = io::BufReader::new(file);
WordReader {
reader : reader,
EOF : false,
buffers : vec![],
curr_line : 0,
str_slices : VecDeque::new(),
curr_slice : None
}
}
pub(super) fn next_word(&mut self) -> Option<(&str, Cursor)> {
// if there are no more words, attempt to read more content
// from the file
if self.str_slices.is_empty() {
self.buffers.clear();
if self.EOF {return None}
let num_buffers = 10;
for buf_idx in 0..num_buffers {
self.buffers.push(String::new());
self.curr_line += 1;
let bytes_read = self.reader.read_line(&mut self.buffers[buf_idx]).unwrap();
// if we've reached the end of the file on the first attempt to read
// a line in this for loop, no further attempts are necessary and we
if bytes_read == 0 {
self.EOF = true;
break;
}
let mut words = self.buffers[buf_idx].split_ascii_whitespace();
for word in words.enumerate() {
let (word_idx, word) = word;
let position = Cursor(Line(self.curr_line), Word(word_idx + 1));
self.str_slices.push_back((word.as_ptr(), word.len(), position))
}
}
}
// if after we've attempted to read in more content from the file,
// there are still no words...
if self.str_slices.is_empty() {
return None
}
// if we make it here, we return the next word
unsafe {
let (ptr, len, position) = self.str_slices.pop_front().unwrap();
let slice = slice::from_raw_parts(ptr, len);
self.curr_slice = Some((ptr, len, position.clone()));
return Some((str::from_utf8(slice).unwrap(), position));
};
}
pub(super) fn curr_word(&mut self) -> Option<(&str, Cursor)> {
match &self.curr_slice {
Some(slice) => {
unsafe {
let (ptr, len, position) = slice.clone();
let slice = slice::from_raw_parts(ptr, len);
Some((str::from_utf8(slice).unwrap(), position))
}
}
None => {None}
}
}
}

144
src/vcd/types.rs Normal file
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@ -0,0 +1,144 @@
use chrono::prelude::*;
#[derive(Debug)]
pub(super) struct Version(pub String);
#[derive(Debug)]
pub(super) enum Timescale {fs, ps, ns, us, ms, s, unit}
#[derive(Debug)]
pub(super) struct Metadata {
pub(super) date : Option<DateTime<Utc>>,
pub(super) version : Option<Version>,
pub(super) timescale : (Option<u32>, Timescale)}
#[derive(Debug, Copy, Clone)]
pub(super) struct Scope_Idx(pub(super) usize);
#[derive(Debug, Copy, Clone)]
pub(super) struct Signal_Idx(pub(super) usize);
#[derive(Debug, Copy, Clone)]
pub(super) struct TimelineIdx(pub(super) u32);
#[derive(Debug, Copy, Clone)]
pub struct StartIdx(pub(super) u32);
#[derive(Debug)]
pub(super) enum Sig_Type {Integer, Parameter, Real, Reg, Str, Wire, Tri1, Time}
#[derive(Debug)]
pub(super) enum Signal{
Data{
name : String,
sig_type : Sig_Type,
// I've seen a 0 bit signal parameter in a xilinx
// simulation before that gets assigned 1 bit values.
// I consider this to be bad behavior. We capture such
// errors in the following type.
signal_error : Option<String>,
num_bits : Option<usize>,
// TODO : may be able to remove self_idx
self_idx : Signal_Idx,
// we could encounter a mix of pure values and strings
// for the same signal timeline
u8_timeline : Vec<u8>,
u8_timeline_markers : Vec<(TimelineIdx)>,
string_timeline : Vec<String>,
string_timeline_markers : Vec<(TimelineIdx)>,
scope_parent : Scope_Idx},
Alias{
name : String,
signal_alias : Signal_Idx}
}
#[derive(Debug)]
pub(super) struct Scope {
pub(super) name : String,
pub(super) parent_idx : Option<Scope_Idx>,
pub(super) self_idx : Scope_Idx,
pub(super) child_signals : Vec<Signal_Idx>,
pub(super) child_scopes : Vec<Scope_Idx>}
// TODO: document how timeline is represented
#[derive(Debug)]
pub struct VCD {
pub(super) metadata : Metadata,
pub timeline : Vec<u8>,
pub timeline_markers : Vec<StartIdx>,
pub(super) all_signals : Vec<Signal>,
pub(super) all_scopes : Vec<Scope>,
pub(super) scope_roots : Vec<Scope_Idx>}
impl VCD {
// TODO : make this a generic traversal function that applies specified
// functions upon encountering scopes and signals
fn print_scope_tree(
&self,
root_scope_idx : Scope_Idx,
depth : usize)
{
let all_scopes = &self.all_scopes;
let all_signals = &self.all_signals;
let indent = " ".repeat(depth * 4);
let Scope_Idx(root_scope_idx) = root_scope_idx;
let root_scope = &all_scopes[root_scope_idx];
let root_scope_name = &root_scope.name;
println!("{indent}scope: {root_scope_name}");
for Signal_Idx(ref signal_idx) in &root_scope.child_signals {
let child_signal = &all_signals[*signal_idx];
let name = match child_signal {
Signal::Data{name, ..} => {name}
Signal::Alias{name, ..} => {name}
};
println!("{indent} - sig: {name}")
}
println!();
for scope_idx in &root_scope.child_scopes {
self.print_scope_tree(*scope_idx, depth+1);
}
}
pub fn print_scopes(&self) {
for scope_root in &self.scope_roots {
self.print_scope_tree(*scope_root, 0);
}
}
pub fn print_longest_signal(&self) {
let mut idx = 0usize;
let mut max_len = 0usize;
let mut signal_name = String::new();
for signal in &self.all_signals {
match signal {
Signal::Alias {..} => {}
Signal::Data {
name,
sig_type,
num_bits,
self_idx,
u8_timeline,
.. } => {
if u8_timeline.len() > max_len {
max_len = u8_timeline.len();
let Signal_Idx(idx_usize) = self_idx;
idx = *idx_usize;
signal_name = name.clone();
}
}
}
}
dbg!((idx, max_len, signal_name));
}
}

287
test-vcd-files/amaranth/up_counter.vcd Normal file
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@ -0,0 +1,287 @@
$comment Generated by Amaranth $end
$date 2022-07-13 18:48:57.685239 $end
$timescale 1 ps $end
$scope module bench $end
$scope module top $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 # ovf $end
$var wire 16 $ count $end
$var string 1 % state $end
$var wire 1 & en $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0!
0"
0#
b0 $
sTOP/0 %
0&
$end
#500000
1!
#1000000
0!
#1500000
1!
#2000000
0!
#2500000
1!
#3000000
0!
#3500000
1!
#4000000
0!
#4500000
1!
#5000000
0!
#5500000
1!
#6000000
0!
#6500000
1!
#7000000
0!
#7500000
1!
#8000000
0!
#8500000
1!
#9000000
0!
#9500000
1!
#10000000
0!
#10500000
1!
#11000000
0!
#11500000
1!
#12000000
0!
#12500000
1!
#13000000
0!
#13500000
1!
#14000000
0!
#14500000
1!
#15000000
0!
#15500000
1!
#16000000
0!
#16500000
1!
#17000000
0!
#17500000
1!
#18000000
0!
#18500000
1!
#19000000
0!
#19500000
1!
#20000000
0!
#20500000
1!
#21000000
0!
#21500000
1!
#22000000
0!
#22500000
1!
#23000000
0!
#23500000
1!
#24000000
0!
#24500000
1!
#25000000
0!
#25500000
1!
#26000000
0!
#26500000
1!
#27000000
0!
#27500000
1!
#28000000
0!
#28500000
1!
#29000000
0!
#29500000
1!
#30000000
0!
#30500000
1&
1!
#31000000
0!
#31500000
sBOTTOM/2 %
b1 $
1!
#32000000
0!
#32500000
b10 $
1!
#33000000
0!
#33500000
b11 $
1!
#34000000
0!
#34500000
b100 $
1!
#35000000
0!
#35500000
b101 $
1!
#36000000
0!
#36500000
b110 $
1!
#37000000
0!
#37500000
b111 $
1!
#38000000
0!
#38500000
b1000 $
1!
#39000000
0!
#39500000
b1001 $
1!
#40000000
0!
#40500000
b1010 $
1!
#41000000
0!
#41500000
b1011 $
1!
#42000000
0!
#42500000
b1100 $
1!
#43000000
0!
#43500000
b1101 $
1!
#44000000
0!
#44500000
b1110 $
1!
#45000000
0!
#45500000
b1111 $
1!
#46000000
0!
#46500000
b10000 $
1!
#47000000
0!
#47500000
b10001 $
1!
#48000000
0!
#48500000
b10010 $
1!
#49000000
0!
#49500000
b10011 $
1!
#50000000
0!
#50500000
b10100 $
1!
#51000000
0!
#51500000
b10101 $
1!
#52000000
0!
#52500000
b10110 $
1!
#53000000
0!
#53500000
b10111 $
1!
#54000000
0!
#54500000
b11000 $
1!
#55000000
0!
#55500000
1#
b11001 $
1!
#56000000
0!
#56500000
sTOP/0 %
0#
b0 $
1!
#57000000
0!
#57500000
sBOTTOM/2 %
b1 $
1!
#58000000

21
test-vcd-files/sources.csv
View file

@ -1,4 +1,17 @@
Icarus,Verilator,GHDL,VCS,QuestaSim,ModelSim,Quartus,SystemC,Treadle,Aldec,Riviera-PRO,MyHDL,ncsim,xilinx_isim,vivado,GTKWave-Analyzer Icarus,https://github.com/dpretet/vcd/blob/master/test1.vcd,https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd,https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd
https://github.com/dpretet/vcd/blob/master/test1.vcd,https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd,https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd,https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd,https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd,https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd,https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd,https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd,https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd,https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd,https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd,https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd,https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd,https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd,https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd,https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd Verilator,https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd,https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd,
https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd,https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd,https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd,https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd,https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd,https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd,,https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd,,,,https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd,,https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd,https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd, GHDL,https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd,https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd,https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd
https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd,,https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd,https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd,,,,,,,,https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd,,https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd,, VCS,https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd,https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd,https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd
QuestaSim,https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd,https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd,
ModelSim,https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd,https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd,
Quartus,https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd,,
SystemC,https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd,https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd,
Treadle,https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd,,
Aldec,https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd,,
Riviera-PRO,https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd,,
MyHDL,https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd,https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd,https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd
ncsim,https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd,,
xilinx_isim,https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd,https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd,https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd
vivado,https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd,https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd,
GTKWave-Analyzer,https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd,,
Amaranth,Locally Simulated File,,
1 Icarus Verilator https://github.com/dpretet/vcd/blob/master/test1.vcd GHDL https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd VCS https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd QuestaSim ModelSim Quartus SystemC Treadle Aldec Riviera-PRO MyHDL ncsim xilinx_isim vivado GTKWave-Analyzer
2 https://github.com/dpretet/vcd/blob/master/test1.vcd Verilator https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd
3 https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd GHDL https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd
4 https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd VCS https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd
5 QuestaSim https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd
6 ModelSim https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd
7 Quartus https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd
8 SystemC https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd
9 Treadle https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd
10 Aldec https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd
11 Riviera-PRO https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd
12 MyHDL https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd
13 ncsim https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd
14 xilinx_isim https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd
15 vivado https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd
16 GTKWave-Analyzer https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd
17 Amaranth Locally Simulated File