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Add all signal types in standard

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This commit is contained in:
Oscar Gustafsson 2023-10-09 14:04:59 +02:00
parent 6c76a066e3
commit b576e1b57d
2 changed files with 39 additions and 5 deletions
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28
src/vcd/parse/scopes.rs
View file

@ -23,27 +23,49 @@ pub(super) fn parse_var<R: std::io::Read>(
) -> Result<(), String> { ) -> Result<(), String> {
let (word, cursor) = next_word!(word_reader)?; let (word, cursor) = next_word!(word_reader)?;
let expected_types = [ let expected_types = [
"event",
"integer", "integer",
"parameter", "parameter",
"real", "real",
"realtime",
"reg", "reg",
"string", "string",
"wire", "supply0",
"tri1", "supply1",
"time", "time",
"tri",
"triand",
"trior",
"trireg",
"tri0",
"tri1",
"wand",
"wire",
"wor",
]; ];
// $var parameter 3 a IDLE $end // $var parameter 3 a IDLE $end
// ^^^^^^^^^ - var_type // ^^^^^^^^^ - var_type
let var_type = match word { let var_type = match word {
"event" => Ok(SigType::Event),
"integer" => Ok(SigType::Integer), "integer" => Ok(SigType::Integer),
"parameter" => Ok(SigType::Parameter), "parameter" => Ok(SigType::Parameter),
"real" => Ok(SigType::Real), "real" => Ok(SigType::Real),
"realtime" => Ok(SigType::RealTime),
"reg" => Ok(SigType::Reg), "reg" => Ok(SigType::Reg),
"string" => Ok(SigType::Str), "string" => Ok(SigType::Str),
"wire" => Ok(SigType::Wire), "supply0" => Ok(SigType::Supply0),
"supply1" => Ok(SigType::Supply1),
"tri" => Ok(SigType::Tri),
"triand" => Ok(SigType::TriAnd),
"trior" => Ok(SigType::TriOr),
"trireg" => Ok(SigType::TriReg),
"tri0" => Ok(SigType::Tri0),
"tri1" => Ok(SigType::Tri1), "tri1" => Ok(SigType::Tri1),
"time" => Ok(SigType::Time), "time" => Ok(SigType::Time),
"wand" => Ok(SigType::WAnd),
"wire" => Ok(SigType::Wire),
"wor" => Ok(SigType::WOr),
_ => { _ => {
let err = format!( let err = format!(
"Error near {}:{} \ "Error near {}:{} \

16
src/vcd/signal.rs
View file

@ -13,14 +13,25 @@ pub struct LsbIdxOfTmstmpValOnTmln(pub(super) u32);
#[derive(Debug)] #[derive(Debug)]
pub enum SigType { pub enum SigType {
Event,
Integer, Integer,
Parameter, Parameter,
Real, Real,
RealTime,
Reg, Reg,
Str, Str,
Wire, Supply0,
Tri1, Supply1,
Time, Time,
Tri,
TriAnd,
TriOr,
TriReg,
Tri0,
Tri1,
WAnd,
Wire,
WOr,
} }
#[derive(Debug, PartialEq)] #[derive(Debug, PartialEq)]
@ -66,6 +77,7 @@ impl<'a> Signal<'a> {
.query_string_val_on_tmln(desired_time, &vcd.tmstmps_encoded_as_u8s, &vcd.all_signals) .query_string_val_on_tmln(desired_time, &vcd.tmstmps_encoded_as_u8s, &vcd.all_signals)
.map(|(val, _)| val) .map(|(val, _)| val)
} }
pub fn query_num_val_on_tmln( pub fn query_num_val_on_tmln(
&self, &self,
desired_time: &BigUint, desired_time: &BigUint,