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Initial SystemVerilog/fst2vcd support

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This commit is contained in:
Oscar Gustafsson 2024-01-07 11:54:40 +01:00
parent de897a5010
commit 909cca2508
5 changed files with 61 additions and 36 deletions
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3
tests/files.rs
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@ -5,8 +5,9 @@
// TODO: we should eventually be able to only test on just
// the files const
pub const FILES: [&str; 31] = [
pub const FILES: [&str; 32] = [
"./tests/vcd-files/aldec/SPI_Write.vcd",
"./tests/vcd-files/fst2vcd/logic.vcd",
"./tests/vcd-files/ghdl/alu.vcd",
"./tests/vcd-files/ghdl/idea.vcd",
"./tests/vcd-files/ghdl/pcpu.vcd",