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Initial SystemVerilog/fst2vcd support

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This commit is contained in:
Oscar Gustafsson 2024-01-07 11:54:40 +01:00
parent de897a5010
commit 909cca2508
5 changed files with 61 additions and 36 deletions
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2
examples/vcd.rs
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@ -73,7 +73,7 @@ fn main() -> std::io::Result<()> {
let timestamps = vec![31499_000u32, 31500_000u32, 57760_000u32];
for timestamp in timestamps {
let time = num::BigUint::from(timestamp);
let val = state_signal.query_string_val_on_tmln(&time, &vcd).unwrap();
let val = state_signal.query_val_on_tmln(&time, &vcd).unwrap();
println!("Signal `{name}` has value `{val}` at time `{time}`");
}