seems to be able to parse signal tree

2022-07-14 16:46:11 -04:00 · 2022-07-14 16:46:11 -04:00 · 8bcd2bc8ec
parent 49d103fd56
commit 8bcd2bc8ec
7 changed files with 611 additions and 54 deletions
--- a/.gitignore
+++ b/.gitignore
@ -1,2 +1,40 @@
 /target
 Cargo.lock
+
+# Created by https://www.toptal.com/developers/gitignore/api/macos
+# Edit at https://www.toptal.com/developers/gitignore?templates=macos
+
+### macOS ###
+# General
+.DS_Store
+.AppleDouble
+.LSOverride
+
+# Icon must end with two \r
+Icon
+
+
+# Thumbnails
+._*
+
+# Files that might appear in the root of a volume
+.DocumentRevisions-V100
+.fseventsd
+.Spotlight-V100
+.TemporaryItems
+.Trashes
+.VolumeIcon.icns
+.com.apple.timemachine.donotpresent
+
+# Directories potentially created on remote AFP share
+.AppleDB
+.AppleDesktop
+Network Trash Folder
+Temporary Items
+.apdisk
+
+### macOS Patch ###
+# iCloud generated files
+*.icloud
+
+# End of https://www.toptal.com/developers/gitignore/api/macos
--- a/src/main.rs
+++ b/src/main.rs
@ -18,7 +18,7 @@ fn main() -> std::io::Result<()> {


    let file = File::open(&args.path)?;
-    parse_vcd(file);
+    parse_vcd(file).unwrap();

    Ok(())
 }
--- a/src/vcd/parse.rs
+++ b/src/vcd/parse.rs
@ -1,6 +1,7 @@
 use chrono::prelude::*;
 use itertools::Itertools;
-use std::fs::File;
+use std::{fs::File};
+use std::collections::{BTreeMap, HashMap};
 use ::function_name::named;

 use super::*;
@ -14,43 +15,251 @@ use types::*;
 mod metadata;
 use metadata::*;

-// use function_name::named;
+#[named]
+fn parse_var<'a>(
+    word_reader      : &mut WordReader,
+    parent_scope_idx : Scope_Idx,
+    vcd              : &'a mut VCD,
+    signal_map       : &mut HashMap<String, Signal_Idx>
+) -> Result<(), String> {
+    let err = format!("reached end of file without parser leaving {}", function_name!());
+    let (word, cursor) = word_reader.next_word().ok_or(&err)?;
+    let expected_types = "[integer, parameter, real, reg, string, wire]";
+
+    // $var parameter 3 a IDLE $end
+    //      ^^^^^^^^^ - var_type
+    let var_type = match word {
+        "integer"    => {Ok(Sig_Type::Integer)}
+        "parameter"  => {Ok(Sig_Type::Parameter)}
+        "real"       => {Ok(Sig_Type::Real)}
+        "reg"        => {Ok(Sig_Type::Reg)}
+        "string"     => {Ok(Sig_Type::Str)}
+        "wire"       => {Ok(Sig_Type::Wire)}
+        _ => {
+            let err = format!("found keyword `{word}` but expected one of {expected_types} on {cursor:?}");
+            Err(err)
+        }
+    }?;
+
+    let (word, cursor) = word_reader.next_word().ok_or(&err)?;
+    let parse_err = format!("failed to parse as usize on {cursor:?}");
+
+    // $var parameter 3 a IDLE $end
+    //                ^ - no_bits
+    let no_bits = match var_type {
+        Sig_Type::Integer | Sig_Type::Parameter |
+        Sig_Type::Real    | Sig_Type::Reg       |
+        Sig_Type::Wire => {
+            let no_bits = word.parse::<usize>().expect(parse_err.as_str());
+            Some(no_bits)
+        }
+        // for strings, we don't really care what the number of bits is
+        _ => {None}
+    };
+
+    // $var parameter 3 a IDLE $end
+    //                  ^ - signal_alias
+    let (word, cursor) = word_reader.next_word().ok_or(&err)?;
+    let signal_alias = word.to_string();
+
+    // $var parameter 3 a IDLE $end
+    //                    ^^^^ - full_signal_name(can extend until $end)
+    let mut full_signal_name = Vec::<String>::new();
+    loop {
+        let (word, cursor) = word_reader.next_word().ok_or(&err)?;
+        match word {
+            "$end" => {break}
+            _      => {full_signal_name.push(word.to_string())}
+        }
+    }
+    let full_signal_name = full_signal_name.join(" ");
+
+    // Is the current variable an alias to a signal already encountered?
+    // if so, handle ref_signal_idx accordingly, if not, add signal to hash
+    // map
+    let (signal, signal_idx) = match signal_map.get(&signal_alias) {
+        Some(ref_signal_idx) => {
+            let signal_idx = Signal_Idx(vcd.all_signals.len());
+            let signal = Signal::Alias{
+                name: full_signal_name,
+                signal_alias: *ref_signal_idx};
+            (signal, signal_idx)
+        }
+        None => {
+            let signal_idx = Signal_Idx(vcd.all_signals.len());
+            signal_map.insert(signal_alias.to_string(), signal_idx);
+            let signal = Signal::Data{
+                name: full_signal_name,
+                sig_type: var_type,
+                num_bits: no_bits,
+                self_idx: signal_idx,
+                timeline: BTreeMap::new(),
+                scope_parent: parent_scope_idx };
+            (signal, signal_idx)
+        }
+    };
+
+    vcd.all_signals.push(signal);
+    let Scope_Idx(parent_scope_idx_usize) = parent_scope_idx;
+    let parent_scope = vcd.all_scopes.get_mut(parent_scope_idx_usize).unwrap();
+    parent_scope.child_signals.push(signal_idx);
+
+    Ok(())
+}

 #[named]
 fn parse_signal_tree<'a>(
    word_reader      : &mut WordReader,
-    vcd         : &'a mut VCD
-) -> Result<&'a mut VCD, String> {
-    let err : Result<&'a mut VCD, String> = Err(format!("reached end of file without parser leaving {}", function_name!()));
-    // we assume we've already seen a `$scope` once
-    // by the time we reach this function
-    // let scope_name = 
-    loop {
-        let word = word_reader.next_word();
+    parent_scope_idx : Option<Scope_Idx>,
+    vcd              : &'a mut VCD,
+    signal_map       : &mut HashMap<String, Signal_Idx>
+) -> Result<(), String> {

-        // if there isn't another word left in the file, then we exit
-        if word.is_none() {
-            return err;
+    // $scope module reg_mag_i $end
+    //        ^^^^^^ - module keyword
+    let err = format!("reached end of file without parser leaving {}", function_name!());
+    ident(word_reader, "module")?;
+
+    // $scope module reg_mag_i $end
+    //               ^^^^^^^^^ - scope name
+    let (scope_name, _) = word_reader.next_word().ok_or(err)?;
+
+    let curr_scope_idx = Scope_Idx(vcd.all_scopes.len());
+    
+    // register this scope as a child of the current parent scope
+    // if there is a parent scope
+    match parent_scope_idx {
+        Some(Scope_Idx(parent_scope_idx)) => {
+            let parent_scope = vcd.all_scopes.get_mut(parent_scope_idx).unwrap();
+            parent_scope.child_scopes.push(curr_scope_idx);
+        }
+        None => {}
+    }
+
+    // add this scope to list of existing scopes
+    vcd.all_scopes.push(
+        Scope {
+            name: scope_name.to_string(),
+            parent_idx: parent_scope_idx,
+            self_idx: curr_scope_idx,
+            child_signals: vec![],
+            child_scopes: vec![]
+        }
+    );
+
+    // $scope module reg_mag_i $end
+    //                         ^^^^ - end keyword
+    ident(word_reader, "$end")?;
+
+    let err = format!("reached end of file without parser leaving {}", function_name!());
+    loop {
+        let (word, cursor) = word_reader.next_word().ok_or(&err)?;
+        let ParseResult{matched, residual} = tag(word, "$");
+        match matched {
+            // we hope that this word stars with a `$`
+            "$" =>  {
+                match residual {
+                    "scope" => {
+                        // recursive - parse inside of current scope tree
+                        parse_signal_tree(word_reader, Some(curr_scope_idx), vcd, signal_map);
+                    }
+                    "var" => {
+                        parse_var(word_reader, curr_scope_idx, vcd, signal_map)?;
+                    }
+                    "upscope" => {
+                        ident(word_reader, "$end")?;
+                        break
+                    }
+                    _ => {
+                        let err = format!("found keyword `{residual}` but expected `$scope`, `$var`, or `$upscope` on {cursor:?}");
+                        return Err(err)
                    }
                }
-    Ok(vcd)
+            }
+            _ => {
+                let err = format!("found keyword `{matched}` but expected `$` on {cursor:?}");
+                return Err(err)
+            }
+        }
+    }
+
+    // TODO : remove the following Ok(()) once we add loop above
+    Ok(())
 }

+// #[named]
+// fn parse_signal_tree_outer<'a>(
+//     word_reader : &mut WordReader,
+//     vcd         : &'a mut VCD,
+//     signal_map  : &mut HashMap<String, Signal_Idx>
+// ) -> Result<(), String> {
+//     // We assume we've already seen a `$scope` once by the time we reach this function,
+//     // that why its call `parse_signal_tree_outer` and not just `parse_signal_tree`.
+//     // If our WordReader had a `putback` function, we wouldn't need to have a 
+//     // `parse_signal_tree_outer`.

-pub fn parse_vcd(file : File) {
+//     // the current scope is the parent scope
+
+//     // $scope module reg_mag_i $end
+//     //        ^^^^^^ - module keyword
+//     let err = format!("reached end of file without parser leaving {}", function_name!());
+//     ident(word_reader, "module")?;
+
+//     // $scope module reg_mag_i $end
+//     //               ^^^^^^^^^ - scope name
+//     let (scope_name, _) = word_reader.next_word().ok_or(err)?;
+
+//     let curr_scope_idx = Scope_Idx(vcd.all_scopes.len());
+    
+//     // register this scope as a child of the current parent scope
+//     let Scope_Idx(parent_scope_idx_usize) = parent_scope_idx;
+//     let parent_scope = vcd.all_scopes.get_mut(parent_scope_idx_usize).unwrap();
+//     parent_scope.child_scopes.push(curr_scope_idx);
+
+//     vcd.all_scopes.push(
+//         Scope {
+//             name: scope_name.to_string(),
+//             parent_idx: parent_scope_idx,
+//             self_idx: curr_scope_idx,
+//             child_signals: vec![],
+//             child_scopes: vec![]
+//         }
+//     );
+
+//     // $scope module reg_mag_i $end
+//     //                         ^^^^ - end keyword
+//     ident(word_reader, "$end")?;
+
+//     // recursive - parse inside of current scope tree
+//     parse_signal_tree(word_reader, curr_scope_idx, vcd, signal_map);
+
+//     // ascend from parsing inside of current scope tree, expect $upscope $end
+//     ident(word_reader, "$upscope")?;
+//     ident(word_reader, "$end")?;
+
+//     Ok(())
+// }
+
+
+pub fn parse_vcd(file : File) -> Result<(), String> {
    let mut word_gen = WordReader::new(file);

-    let header = parse_metadata(&mut word_gen).unwrap();
+    let header = parse_metadata(&mut word_gen)?;
    dbg!(&header);

    // let (word, cursor) = word_gen.next_word().unwrap();
    // cursor.error(word).unwrap();
+    let mut signal_map = std::collections::HashMap::new();

    let mut vcd = VCD{
        metadata: header,
        all_signals: vec![],
-        all_scopes: vec![]
+        all_scopes: vec![],
    };
+
+    parse_signal_tree(&mut word_gen, None, &mut vcd, &mut signal_map)?;
+    dbg!(&vcd.all_scopes);
+    Ok(())
 }

 #[cfg(test)]
--- a/src/vcd/parse/combinator_atoms.rs
+++ b/src/vcd/parse/combinator_atoms.rs
@ -1,4 +1,5 @@
 use super::types::ParseResult;
+use super::reader::WordReader;

 pub(super) fn digit(chr : u8) -> bool {
    let zero = b'0' as u8;
@ -82,3 +83,22 @@ pub(super) fn tag<'a>(word : &'a str, pattern : &'a str) -> ParseResult<'a> {
            residual : &word[new_start..]
        };
 }
+
+pub(super) fn ident(
+    word_reader : &mut WordReader,
+    keyword : &str, 
+) -> Result<(), String> {
+    // let keyword = "module";
+
+    let err : Result<(), String> = Err(format!("reached end of file without parser leaving ident"));
+    let word = word_reader.next_word();
+    let (word, cursor) = word.ok_or(err).unwrap();
+
+    if word == keyword {
+        return Ok(())
+    }
+    else {
+        let err = format!("found keyword `{word}` but expected `{keyword}` on {cursor:?}");
+        return Err(err)
+    }
+}
--- a/src/vcd/types.rs
+++ b/src/vcd/types.rs
@ -1,4 +1,4 @@
-use std::collections::BTreeMap;
+use std::collections::{BTreeMap, HashMap};
 use chrono::prelude::*;
 use num::BigInt;

@ -14,46 +14,49 @@ pub(super) struct Metadata {
    pub(super) version   : Option<Version>,
    pub(super) timescale : (Option<u32>, Timescale)}

-#[derive(Debug)]
-pub(super) struct Scope_Idx(usize);
+#[derive(Debug, Copy, Clone)]
+pub(super) struct Scope_Idx(pub(super) usize);
+
+#[derive(Debug, Copy, Clone)]
+pub(super) struct Signal_Idx(pub(super) usize);

 #[derive(Debug)]
-pub(super) struct Signal_Idx(usize);
+pub(super) enum Sig_Type {Integer, Parameter, Real, Reg, Str, Wire,}

 #[derive(Debug)]
-pub(super) enum SignalGeneric{
-    Signal{
+pub(super) enum Sig_Value {
+    Numeric(BigInt),
+    NonNumeric(String)}
+
+#[derive(Debug)]
+pub(super) enum Signal{
+    Data{
         name         : String,
-        timeline       : BTreeMap<BigInt, BigInt>,
+         sig_type     : Sig_Type,
+         num_bits     : Option<usize>,
+         // TODO : may be able to remove self_idx
+         self_idx     : Signal_Idx,
+         timeline     : BTreeMap<BigInt, Sig_Value>,
         scope_parent : Scope_Idx},
-    SignalAlias{
+    Alias{
         name         : String,
         signal_alias : Signal_Idx}
 }

 #[derive(Debug)]
 pub(super) struct Scope {
-    name          : String,
-    child_signals : Vec<Signal_Idx>,
-    child_scopes  : Vec<Scope_Idx>}
+    pub(super) name          : String,
+
+    pub(super) parent_idx    : Option<Scope_Idx>,
+    // TODO : may be able to remove self_idx
+    pub(super) self_idx      : Scope_Idx,
+
+    pub(super) child_signals : Vec<Signal_Idx>,
+    pub(super) child_scopes  : Vec<Scope_Idx>}


 #[derive(Debug)]
 pub struct VCD {
    pub(super) metadata    : Metadata,
-    pub(super) all_signals : Vec<SignalGeneric>,
-    // the root scope should always be placed at index 0
+    pub(super) all_signals : Vec<Signal>,
    pub(super) all_scopes  : Vec<Scope>}
-
-impl VCD {
-    pub fn new() -> Self {
-        let metadata = Metadata {
-            date      : None,
-            version   : None,
-            timescale : (None, Timescale::unit)};
-        VCD {
-            metadata    : metadata,
-            all_signals : Vec::<SignalGeneric>::new(),
-            all_scopes  : Vec::<Scope>::new()}
-        }
-    }
--- a/test-vcd-files/amaranth/up_counter.vcd
+++ b/test-vcd-files/amaranth/up_counter.vcd
@ -0,0 +1,287 @@
+$comment Generated by Amaranth $end
+$date 2022-07-13 18:48:57.685239 $end
+$timescale 1 ps $end
+$scope module bench $end
+$scope module top $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$var wire 1 # ovf $end
+$var wire 16 $ count $end
+$var string 1 % state $end
+$var wire 1 & en $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0!
+0"
+0#
+b0 $
+sTOP/0 %
+0&
+$end
+#500000
+1!
+#1000000
+0!
+#1500000
+1!
+#2000000
+0!
+#2500000
+1!
+#3000000
+0!
+#3500000
+1!
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+0!
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+1!
+#30000000
+0!
+#30500000
+1&
+1!
+#31000000
+0!
+#31500000
+sBOTTOM/2 %
+b1 $
+1!
+#32000000
+0!
+#32500000
+b10 $
+1!
+#33000000
+0!
+#33500000
+b11 $
+1!
+#34000000
+0!
+#34500000
+b100 $
+1!
+#35000000
+0!
+#35500000
+b101 $
+1!
+#36000000
+0!
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+b110 $
+1!
+#37000000
+0!
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+b111 $
+1!
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+b1000 $
+1!
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+1!
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+1!
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+b1011 $
+1!
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+b1100 $
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+b1110 $
+1!
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+b1111 $
+1!
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+0!
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+b10000 $
+1!
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+0!
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+b10001 $
+1!
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+0!
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+b10010 $
+1!
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+1!
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+b10100 $
+1!
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+b10101 $
+1!
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+0#
+b0 $
+1!
+#57000000
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+sBOTTOM/2 %
+b1 $
+1!
+#58000000
--- a/test-vcd-files/sources.csv
+++ b/test-vcd-files/sources.csv
@ -1,4 +1,4 @@
-Icarus,Verilator,GHDL,VCS,QuestaSim,ModelSim,Quartus,SystemC,Treadle,Aldec,Riviera-PRO,MyHDL,ncsim,xilinx_isim,vivado,GTKWave-Analyzer
-https://github.com/dpretet/vcd/blob/master/test1.vcd,https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd,https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd,https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd,https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd,https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd,https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd,https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd,https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd,https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd,https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd,https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd,https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd,https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd,https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd,https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd
-https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd,https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd,https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd,https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd,https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd,https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd,,https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd,,,,https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd,,https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd,https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd,
-https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd,,https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd,https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd,,,,,,,,https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd,,https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd,,
+Icarus,Verilator,GHDL,VCS,QuestaSim,ModelSim,Quartus,SystemC,Treadle,Aldec,Riviera-PRO,MyHDL,ncsim,xilinx_isim,vivado,GTKWave-Analyzer,Amaranth
+https://github.com/dpretet/vcd/blob/master/test1.vcd,https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd,https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd,https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd,https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd,https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd,https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd,https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd,https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd,https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd,https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd,https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd,https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd,https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd,https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd,https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd,Locally Simulated File
+https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd,https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd,https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd,https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd,https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd,https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd,,https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd,,,,https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd,,https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd,https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd,,
+https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd,,https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd,https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd,,,,,,,,https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd,,https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd,,,