From 8b9114499e48c13c9eac66ef11edb510fee8ca9e Mon Sep 17 00:00:00 2001 From: Void User Date: Thu, 23 Jun 2022 20:52:39 -0400 Subject: [PATCH] a bit of restructuring to support more modular tests --- src/test/files.rs | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/test/files.rs diff --git a/src/test/files.rs b/src/test/files.rs new file mode 100644 index 0000000..e658a97 --- /dev/null +++ b/src/test/files.rs @@ -0,0 +1,32 @@ +pub const files : [&str; 24] = [ + "./test-vcd-files/aldec/SPI_Write.vcd", + "./test-vcd-files/ghdl/alu.vcd", + "./test-vcd-files/ghdl/idea.vcd", + "./test-vcd-files/ghdl/pcpu.vcd", + "./test-vcd-files/gtkwave-analyzer/perm_current.vcd", + "./test-vcd-files/icarus/CPU.vcd", + "./test-vcd-files/icarus/rv32_soc_TB.vcd", + "./test-vcd-files/icarus/test1.vcd", + "./test-vcd-files/model-sim/CPU_Design.msim.vcd", + "./test-vcd-files/model-sim/clkdiv2n_tb.vcd", + "./test-vcd-files/my-hdl/Simple_Memory.vcd", + "./test-vcd-files/my-hdl/sigmoid_tb.vcd", + "./test-vcd-files/my-hdl/top.vcd", + // "./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd", + // "./test-vcd-files/quartus/mipsHardware.vcd", + // "./test-vcd-files/quartus/wave_registradores.vcd", + "./test-vcd-files/questa-sim/dump.vcd", + "./test-vcd-files/questa-sim/test.vcd", + "./test-vcd-files/riviera-pro/dump.vcd", + // "./test-vcd-files/systemc/waveform.vcd", + // "./test-vcd-files/treadle/GCD.vcd", + "./test-vcd-files/vcs/Apb_slave_uvm_new.vcd", + "./test-vcd-files/vcs/datapath_log.vcd", + "./test-vcd-files/vcs/processor.vcd", + "./test-vcd-files/verilator/swerv1.vcd", + "./test-vcd-files/verilator/vlt_dump.vcd", + // "./test-vcd-files/vivado/iladata.vcd", + "./test-vcd-files/xilinx_isim/test.vcd", + "./test-vcd-files/xilinx_isim/test1.vcd", + "./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd" +]; \ No newline at end of file