Yehowshua/FastWaveBackend
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missed some files by committing in the wrong folder

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Void User 2022-06-23 20:54:27 -04:00
parent 8b9114499e
commit 77235a19bc
3 changed files with 7 additions and 34 deletions
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3
src/main.rs
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@ -1,6 +1,9 @@
use std::fs::File;
use clap::Parser;
pub mod test;
use test::*;
pub mod vcd;
use vcd::*;

2
src/test.rs Normal file
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@ -0,0 +1,2 @@
mod files;
pub use files::*;

36
src/vcd/parse.rs
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@ -25,43 +25,11 @@ pub fn parse_vcd(file : File) {
#[cfg(test)]
mod tests {
use super::*;
use crate::test;
use std::fs::File;
#[test]
fn headers() {
let files = vec![
"./test-vcd-files/aldec/SPI_Write.vcd",
"./test-vcd-files/ghdl/alu.vcd",
"./test-vcd-files/ghdl/idea.vcd",
"./test-vcd-files/ghdl/pcpu.vcd",
"./test-vcd-files/gtkwave-analyzer/perm_current.vcd",
"./test-vcd-files/icarus/CPU.vcd",
"./test-vcd-files/icarus/rv32_soc_TB.vcd",
"./test-vcd-files/icarus/test1.vcd",
"./test-vcd-files/model-sim/CPU_Design.msim.vcd",
"./test-vcd-files/model-sim/clkdiv2n_tb.vcd",
"./test-vcd-files/my-hdl/Simple_Memory.vcd",
"./test-vcd-files/my-hdl/sigmoid_tb.vcd",
"./test-vcd-files/my-hdl/top.vcd",
// "./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
// "./test-vcd-files/quartus/mipsHardware.vcd",
// "./test-vcd-files/quartus/wave_registradores.vcd",
"./test-vcd-files/questa-sim/dump.vcd",
"./test-vcd-files/questa-sim/test.vcd",
"./test-vcd-files/riviera-pro/dump.vcd",
// "./test-vcd-files/systemc/waveform.vcd",
// "./test-vcd-files/treadle/GCD.vcd",
"./test-vcd-files/vcs/Apb_slave_uvm_new.vcd",
"./test-vcd-files/vcs/datapath_log.vcd",
"./test-vcd-files/vcs/processor.vcd",
"./test-vcd-files/verilator/swerv1.vcd",
"./test-vcd-files/verilator/vlt_dump.vcd",
// "./test-vcd-files/vivado/iladata.vcd",
"./test-vcd-files/xilinx_isim/test.vcd",
"./test-vcd-files/xilinx_isim/test1.vcd",
"./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
];
for file in files {
for file in test::files {
let metadata = parse_metadata(
&mut WordReader::new(
File::open(file)