test VCD files

test-vcd-files/ghdl/alu.vcd

@@ -0,0 +1,768 @@
+$date
+  Mon Nov 25 19:21:45 2019
+$end
+$version
+  GHDL v0
+$end
+$timescale
+  1 fs
+$end
+$var reg 32 ! op1[31:0] $end
+$var reg 32 " op2[31:0] $end
+$var reg 1 # cin $end
+$var reg 2 $ cmd[1:0] $end
+$var reg 32 % res[31:0] $end
+$var reg 1 & cout $end
+$var reg 1 ' z $end
+$var reg 1 ( n $end
+$var reg 1 ) v $end
+$var reg 1 * vdd $end
+$var reg 1 + vss $end
+$scope module instance $end
+$var reg 32 , op1[31:0] $end
+$var reg 32 - op2[31:0] $end
+$var reg 1 . cin $end
+$var reg 2 / cmd[1:0] $end
+$var reg 32 0 res[31:0] $end
+$var reg 1 1 cout $end
+$var reg 1 2 z $end
+$var reg 1 3 n $end
+$var reg 1 4 v $end
+$var reg 1 5 vdd $end
+$var reg 1 6 vss $end
+$var reg 32 7 res_temp[31:0] $end
+$var reg 1 8 c31 $end
+$var reg 1 9 c_out $end
+$upscope $end
+$enddefinitions $end
+#0
+b01111111111111111111101001111100 !
+b01111001011110100001111000101101 "
+1#
+b00 $
+b11111001011110100001100010101010 %
+0&
+0'
+1(
+1)
+0*
+0+
+b01111111111111111111101001111100 ,
+b01111001011110100001111000101101 -
+1.
+b00 /
+b11111001011110100001100010101010 0
+01
+02
+13
+14
+05
+06
+b11111001011110100001100010101010 7
+18
+09
+#10000
+b11010101010001010001100011100101 !
+b10001001011101010011001010010110 "
+0#
+b01011110101110100100101101111011 %
+1&
+0(
+1)
+b11010101010001010001100011100101 ,
+b10001001011101010011001010010110 -
+0.
+b01011110101110100100101101111011 0
+11
+03
+14
+b01011110101110100100101101111011 7
+08
+19
+#20000
+b00101010001001100010110100100001 !
+b10010101101011010001111100001110 "
+b10111111110100110100110000101111 %
+0&
+1(
+0)
+b00101010001001100010110100100001 ,
+b10010101101011010001111100001110 -
+b10111111110100110100110000101111 0
+01
+13
+04
+b10111111110100110100110000101111 7
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+09
+#30000
+b10101010110101001010000010000001 !
+b00100111101010110100100101011000 "
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+#40000
+b01101000111110110001110101100100 !
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+#50000
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+#60000
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+b01 /
+b00010000010000010000000001001000 0
+b00010000010000010000000001001000 7

test-vcd-files/model-sim/clkdiv2n_tb.vcd

@@ -0,0 +1,292 @@
+$date
+	Sat Dec 26 15:33:14 2020
+$end
+$version
+	ModelSim Version 10.5b
+$end
+$timescale
+	1ns
+$end
+
+$scope module clkdiv2n_tb $end
+$var reg 1 ! clk $end
+$var reg 1 " reset $end
+$var wire 1 # clk_out $end
+
+$scope module t1 $end
+$var parameter 32 $ WIDTH $end
+$var parameter 32 % N $end
+$var wire 1 & clk $end
+$var wire 1 ' reset $end
+$var wire 1 # clk_out $end
+$var reg 3 ( r_reg [2:0] $end
+$var wire 1 ) r_nxt [2] $end
+$var wire 1 * r_nxt [1] $end
+$var wire 1 + r_nxt [0] $end
+$var reg 1 , clk_track $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0!
+x"
+bx (
+x,
+b11 $
+b110 %
+x#
+x+
+x*
+x)
+x'
+0&
+$end
+#5
+1"
+1'
+b0 (
+0,
+1+
+0*
+0)
+0#
+#10
+1!
+1&
+#15
+0"
+0'
+#20
+0!
+0&
+#30
+1!
+1&
+b1 (
+0+
+1*
+#40
+0!
+0&
+#50
+1!
+1&
+b10 (
+1+
+#60
+0!
+0&
+#70
+1!
+1&
+b11 (
+0+
+0*
+1)
+#80
+0!
+0&
+#90
+1!
+1&
+b100 (
+1+
+#100
+0!
+0&
+#110
+1!
+1&
+b101 (
+0+
+1*
+#120
+0!
+0&
+#130
+1!
+1&
+b0 (
+1,
+1+
+0*
+0)
+1#
+#140
+0!
+0&
+#150
+1!
+1&
+b1 (
+0+
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+0&
+#510
+1!
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+b1 (
+0+
+1*

test-vcd-files/quartus/wave_registradores.vcd

@@ -0,0 +1,151 @@
+$date
+     Dec 16, 2020       19:50:58
+$end
+
+$version
+ SystemC 2.3.3-Accellera --- Nov 12 2020 19:12:35
+$end
+
+$timescale
+     1 ps
+$end
+
+$scope module SystemC $end
+$var wire    1  aaaaa  clock       $end
+$var wire    1  aaaab  mi_RegWrite       $end
+$var wire    5  aaaac  i_ReadRegister1 [4:0]  $end
+$var wire    5  aaaad  i_ReadRegister2 [4:0]  $end
+$var wire    5  aaaae  i_WriteRegister [4:0]  $end
+$var wire   32  aaaaf  i_WriteData [31:0]  $end
+$var wire   32  aaaag  o_ReadData1 [31:0]  $end
+$var wire   32  aaaah  o_ReadData2 [31:0]  $end
+$upscope $end
+$enddefinitions  $end
+
+$comment
+All initial values are dumped below at time 0 sec = 0 timescale units.
+$end
+
+$dumpvars
+1aaaaa
+1aaaab
+b0 aaaac
+b0 aaaad
+b1 aaaae
+b1 aaaaf
+b0 aaaag
+b0 aaaah
+$end
+
+#25000
+0aaaaa
+
+#50000
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+b10 aaaaf
+
+#75000
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+
+#100000
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+
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+
+#175000
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+
+#225000
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+
+#275000
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+
+#325000
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+
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+
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+
+#425000
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+
+#450000
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+
+#475000
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+
+#500000
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+
+#525000
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+
+#550000
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+b10 aaaaf
+
+#575000
+0aaaaa
+
+#600000

test-vcd-files/questa-sim/test.vcd

@@ -0,0 +1,478 @@
+$date
+	Wed Jul  7 08:30:24 2021
+$end
+$version
+	QuestaSim Version 2020.1_1
+$end
+$timescale
+	1ns
+$end
+
+$scope module test $end
+$var reg 1 ! clk $end
+$var wire 1 " count [2] $end
+$var wire 1 # count [1] $end
+$var wire 1 $ count [0] $end
+
+$scope module dut $end
+$var reg 3 % count [2:0] $end
+$var wire 1 & clk $end
+$var reg 5 ' Dout [4:0] $end
+$var reg 5 ( Din [4:0] $end
+
+$scope begin init[4] $end
+$var parameter 32 ) i $end
+
+$scope module inst $end
+$var reg 1 * q $end
+$var wire 1 + din $end
+$var wire 1 & clk $end
+$upscope $end
+$upscope $end
+
+$scope begin init[3] $end
+$var parameter 32 , i $end
+
+$scope module inst $end
+$var reg 1 - q $end
+$var wire 1 . din $end
+$var wire 1 & clk $end
+$upscope $end
+$upscope $end
+
+$scope begin init[2] $end
+$var parameter 32 / i $end
+
+$scope module inst $end
+$var reg 1 0 q $end
+$var wire 1 1 din $end
+$var wire 1 & clk $end
+$upscope $end
+$upscope $end
+
+$scope begin init[1] $end
+$var parameter 32 2 i $end
+
+$scope module inst $end
+$var reg 1 3 q $end
+$var wire 1 4 din $end
+$var wire 1 & clk $end
+$upscope $end
+$upscope $end
+
+$scope begin init[0] $end
+$var parameter 32 5 i $end
+
+$scope module inst $end
+$var reg 1 6 q $end
+$var wire 1 7 din $end
+$var wire 1 & clk $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0!
+bx %
+bx '
+bx (
+x6
+x3
+x0
+x-
+x*
+b0 5
+b1 2
+b10 /
+b11 ,
+b100 )
+x$
+x#
+x"
+0&
+x7
+x4
+x1
+x.
+x+
+$end
+#5
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+#196
+b1011 (
+17

test-vcd-files/riviera-pro/dump.vcd

@@ -0,0 +1,936 @@
+$date
+Mon Jul 19 14:17:09 2021
+$end
+$version
+Riviera-PRO Version 2020.04.130.7729
+$end
+$timescale
+1 ps
+$end
+
+$scope module tb_tic_tac_toe $end
+$var wire 2 ! pos_led1 [1:0] $end
+$var wire 2 " pos_led2 [1:0] $end
+$var wire 2 # pos_led3 [1:0] $end
+$var wire 2 $ pos_led4 [1:0] $end
+$var wire 2 % pos_led5 [1:0] $end
+$var wire 2 & pos_led6 [1:0] $end
+$var wire 2 ' pos_led7 [1:0] $end
+$var wire 2 ( pos_led8 [1:0] $end
+$var wire 2 ) pos_led9 [1:0] $end
+$var wire 2 * who [1:0] $end
+$var reg 1 + clock $end
+$var reg 1 , reset $end
+$var reg 1 - play $end
+$var reg 1 . pc $end
+$var reg 4 / computer_position [3:0] $end
+$var reg 4 0 player_position [3:0] $end
+
+$scope module uut $end
+$var wire 1 1 clock $end
+$var wire 1 2 reset $end
+$var wire 1 3 play $end
+$var wire 1 4 pc $end
+$var wire 4 5 computer_position [3:0] $end
+$var wire 4 6 player_position [3:0] $end
+$var wire 2 ! pos1 [1:0] $end
+$var wire 2 " pos2 [1:0] $end
+$var wire 2 # pos3 [1:0] $end
+$var wire 2 $ pos4 [1:0] $end
+$var wire 2 % pos5 [1:0] $end
+$var wire 2 & pos6 [1:0] $end
+$var wire 2 ' pos7 [1:0] $end
+$var wire 2 ( pos8 [1:0] $end
+$var wire 2 ) pos9 [1:0] $end
+$var wire 2 * who [1:0] $end
+$var wire 1 7 PC_en [15] $end
+$var wire 1 8 PC_en [14] $end
+$var wire 1 9 PC_en [13] $end
+$var wire 1 : PC_en [12] $end
+$var wire 1 ; PC_en [11] $end
+$var wire 1 < PC_en [10] $end
+$var wire 1 = PC_en [9] $end
+$var wire 1 > PC_en [8] $end
+$var wire 1 ? PC_en [7] $end
+$var wire 1 @ PC_en [6] $end
+$var wire 1 A PC_en [5] $end
+$var wire 1 B PC_en [4] $end
+$var wire 1 C PC_en [3] $end
+$var wire 1 D PC_en [2] $end
+$var wire 1 E PC_en [1] $end
+$var wire 1 F PC_en [0] $end
+$var wire 1 G PL_en [15] $end
+$var wire 1 H PL_en [14] $end
+$var wire 1 I PL_en [13] $end
+$var wire 1 J PL_en [12] $end
+$var wire 1 K PL_en [11] $end
+$var wire 1 L PL_en [10] $end
+$var wire 1 M PL_en [9] $end
+$var wire 1 N PL_en [8] $end
+$var wire 1 O PL_en [7] $end
+$var wire 1 P PL_en [6] $end
+$var wire 1 Q PL_en [5] $end
+$var wire 1 R PL_en [4] $end
+$var wire 1 S PL_en [3] $end
+$var wire 1 T PL_en [2] $end
+$var wire 1 U PL_en [1] $end
+$var wire 1 V PL_en [0] $end
+$var wire 1 W illegal_move $end
+$var wire 1 X win $end
+$var wire 1 Y computer_play $end
+$var wire 1 Z player_play $end
+$var wire 1 [ no_space $end
+
+$scope module position_reg_unit $end
+$var wire 1 1 clock $end
+$var wire 1 2 reset $end
+$var wire 1 W illegal_move $end
+$var wire 1 > PC_en [8] $end
+$var wire 1 ? PC_en [7] $end
+$var wire 1 @ PC_en [6] $end
+$var wire 1 A PC_en [5] $end
+$var wire 1 B PC_en [4] $end
+$var wire 1 C PC_en [3] $end
+$var wire 1 D PC_en [2] $end
+$var wire 1 E PC_en [1] $end
+$var wire 1 F PC_en [0] $end
+$var wire 1 N PL_en [8] $end
+$var wire 1 O PL_en [7] $end
+$var wire 1 P PL_en [6] $end
+$var wire 1 Q PL_en [5] $end
+$var wire 1 R PL_en [4] $end
+$var wire 1 S PL_en [3] $end
+$var wire 1 T PL_en [2] $end
+$var wire 1 U PL_en [1] $end
+$var wire 1 V PL_en [0] $end
+$var reg 2 \ pos1 [1:0] $end
+$var reg 2 ] pos2 [1:0] $end
+$var reg 2 ^ pos3 [1:0] $end
+$var reg 2 _ pos4 [1:0] $end
+$var reg 2 ` pos5 [1:0] $end
+$var reg 2 a pos6 [1:0] $end
+$var reg 2 b pos7 [1:0] $end
+$var reg 2 c pos8 [1:0] $end
+$var reg 2 d pos9 [1:0] $end
+$upscope $end
+
+
+$scope module win_detect_unit $end
+$var wire 2 ! pos1 [1:0] $end
+$var wire 2 " pos2 [1:0] $end
+$var wire 2 # pos3 [1:0] $end
+$var wire 2 $ pos4 [1:0] $end
+$var wire 2 % pos5 [1:0] $end
+$var wire 2 & pos6 [1:0] $end
+$var wire 2 ' pos7 [1:0] $end
+$var wire 2 ( pos8 [1:0] $end
+$var wire 2 ) pos9 [1:0] $end
+$var wire 1 X winner $end
+$var wire 2 * who [1:0] $end
+$var wire 1 e win1 $end
+$var wire 1 f win2 $end
+$var wire 1 g win3 $end
+$var wire 1 h win4 $end
+$var wire 1 i win5 $end
+$var wire 1 j win6 $end
+$var wire 1 k win7 $end
+$var wire 1 l win8 $end
+$var wire 2 m who1 [1:0] $end
+$var wire 2 n who2 [1:0] $end
+$var wire 2 o who3 [1:0] $end
+$var wire 2 p who4 [1:0] $end
+$var wire 2 q who5 [1:0] $end
+$var wire 2 r who6 [1:0] $end
+$var wire 2 s who7 [1:0] $end
+$var wire 2 t who8 [1:0] $end
+
+$scope module u1 $end
+$var wire 2 ! pos0 [1:0] $end
+$var wire 2 " pos1 [1:0] $end
+$var wire 2 # pos2 [1:0] $end
+$var wire 1 e winner $end
+$var wire 2 m who [1:0] $end
+$var wire 2 u temp0 [1:0] $end
+$var wire 2 v temp1 [1:0] $end
+$var wire 2 w temp2 [1:0] $end
+$var wire 1 x temp3 $end
+$upscope $end
+
+
+$scope module u2 $end
+$var wire 2 $ pos0 [1:0] $end
+$var wire 2 % pos1 [1:0] $end
+$var wire 2 & pos2 [1:0] $end
+$var wire 1 f winner $end
+$var wire 2 n who [1:0] $end
+$var wire 2 y temp0 [1:0] $end
+$var wire 2 z temp1 [1:0] $end
+$var wire 2 { temp2 [1:0] $end
+$var wire 1 | temp3 $end
+$upscope $end
+
+
+$scope module u3 $end
+$var wire 2 ' pos0 [1:0] $end
+$var wire 2 ( pos1 [1:0] $end
+$var wire 2 ) pos2 [1:0] $end
+$var wire 1 g winner $end
+$var wire 2 o who [1:0] $end
+$var wire 2 } temp0 [1:0] $end
+$var wire 2 ~ temp1 [1:0] $end
+$var wire 2 !! temp2 [1:0] $end
+$var wire 1 "! temp3 $end
+$upscope $end
+
+
+$scope module u4 $end
+$var wire 2 ! pos0 [1:0] $end
+$var wire 2 $ pos1 [1:0] $end
+$var wire 2 ' pos2 [1:0] $end
+$var wire 1 h winner $end
+$var wire 2 p who [1:0] $end
+$var wire 2 #! temp0 [1:0] $end
+$var wire 2 $! temp1 [1:0] $end
+$var wire 2 %! temp2 [1:0] $end
+$var wire 1 &! temp3 $end
+$upscope $end
+
+
+$scope module u5 $end
+$var wire 2 " pos0 [1:0] $end
+$var wire 2 % pos1 [1:0] $end
+$var wire 2 ( pos2 [1:0] $end
+$var wire 1 i winner $end
+$var wire 2 q who [1:0] $end
+$var wire 2 '! temp0 [1:0] $end
+$var wire 2 (! temp1 [1:0] $end
+$var wire 2 )! temp2 [1:0] $end
+$var wire 1 *! temp3 $end
+$upscope $end
+
+
+$scope module u6 $end
+$var wire 2 # pos0 [1:0] $end
+$var wire 2 & pos1 [1:0] $end
+$var wire 2 ) pos2 [1:0] $end
+$var wire 1 j winner $end
+$var wire 2 r who [1:0] $end
+$var wire 2 +! temp0 [1:0] $end
+$var wire 2 ,! temp1 [1:0] $end
+$var wire 2 -! temp2 [1:0] $end
+$var wire 1 .! temp3 $end
+$upscope $end
+
+
+$scope module u7 $end
+$var wire 2 ! pos0 [1:0] $end
+$var wire 2 % pos1 [1:0] $end
+$var wire 2 ) pos2 [1:0] $end
+$var wire 1 k winner $end
+$var wire 2 s who [1:0] $end
+$var wire 2 /! temp0 [1:0] $end
+$var wire 2 0! temp1 [1:0] $end
+$var wire 2 1! temp2 [1:0] $end
+$var wire 1 2! temp3 $end
+$upscope $end
+
+
+$scope module u8 $end
+$var wire 2 # pos0 [1:0] $end
+$var wire 2 % pos1 [1:0] $end
+$var wire 2 & pos2 [1:0] $end
+$var wire 1 l winner $end
+$var wire 2 t who [1:0] $end
+$var wire 2 3! temp0 [1:0] $end
+$var wire 2 4! temp1 [1:0] $end
+$var wire 2 5! temp2 [1:0] $end
+$var wire 1 6! temp3 $end
+$upscope $end
+
+$upscope $end
+
+
+$scope module pd1 $end
+$var wire 4 5 in [3:0] $end
+$var wire 1 Y enable $end
+$var wire 1 7 out_en [15] $end
+$var wire 1 8 out_en [14] $end
+$var wire 1 9 out_en [13] $end
+$var wire 1 : out_en [12] $end
+$var wire 1 ; out_en [11] $end
+$var wire 1 < out_en [10] $end
+$var wire 1 = out_en [9] $end
+$var wire 1 > out_en [8] $end
+$var wire 1 ? out_en [7] $end
+$var wire 1 @ out_en [6] $end
+$var wire 1 A out_en [5] $end
+$var wire 1 B out_en [4] $end
+$var wire 1 C out_en [3] $end
+$var wire 1 D out_en [2] $end
+$var wire 1 E out_en [1] $end
+$var wire 1 F out_en [0] $end
+$var reg 16 7! temp1 [15:0] $end
+$upscope $end
+
+
+$scope module pd2 $end
+$var wire 4 6 in [3:0] $end
+$var wire 1 Z enable $end
+$var wire 1 G out_en [15] $end
+$var wire 1 H out_en [14] $end
+$var wire 1 I out_en [13] $end
+$var wire 1 J out_en [12] $end
+$var wire 1 K out_en [11] $end
+$var wire 1 L out_en [10] $end
+$var wire 1 M out_en [9] $end
+$var wire 1 N out_en [8] $end
+$var wire 1 O out_en [7] $end
+$var wire 1 P out_en [6] $end
+$var wire 1 Q out_en [5] $end
+$var wire 1 R out_en [4] $end
+$var wire 1 S out_en [3] $end
+$var wire 1 T out_en [2] $end
+$var wire 1 U out_en [1] $end
+$var wire 1 V out_en [0] $end
+$var reg 16 8! temp1 [15:0] $end
+$upscope $end
+
+
+$scope module imd_unit $end
+$var wire 2 ! pos1 [1:0] $end
+$var wire 2 " pos2 [1:0] $end
+$var wire 2 # pos3 [1:0] $end
+$var wire 2 $ pos4 [1:0] $end
+$var wire 2 % pos5 [1:0] $end
+$var wire 2 & pos6 [1:0] $end
+$var wire 2 ' pos7 [1:0] $end
+$var wire 2 ( pos8 [1:0] $end
+$var wire 2 ) pos9 [1:0] $end
+$var wire 1 > PC_en [8] $end
+$var wire 1 ? PC_en [7] $end
+$var wire 1 @ PC_en [6] $end
+$var wire 1 A PC_en [5] $end
+$var wire 1 B PC_en [4] $end
+$var wire 1 C PC_en [3] $end
+$var wire 1 D PC_en [2] $end
+$var wire 1 E PC_en [1] $end
+$var wire 1 F PC_en [0] $end
+$var wire 1 N PL_en [8] $end
+$var wire 1 O PL_en [7] $end
+$var wire 1 P PL_en [6] $end
+$var wire 1 Q PL_en [5] $end
+$var wire 1 R PL_en [4] $end
+$var wire 1 S PL_en [3] $end
+$var wire 1 T PL_en [2] $end
+$var wire 1 U PL_en [1] $end
+$var wire 1 V PL_en [0] $end
+$var wire 1 W illegal_move $end
+$var wire 1 9! temp1 $end
+$var wire 1 :! temp2 $end
+$var wire 1 ;! temp3 $end
+$var wire 1 <! temp4 $end
+$var wire 1 =! temp5 $end
+$var wire 1 >! temp6 $end
+$var wire 1 ?! temp7 $end
+$var wire 1 @! temp8 $end
+$var wire 1 A! temp9 $end
+$var wire 1 B! temp11 $end
+$var wire 1 C! temp12 $end
+$var wire 1 D! temp13 $end
+$var wire 1 E! temp14 $end
+$var wire 1 F! temp15 $end
+$var wire 1 G! temp16 $end
+$var wire 1 H! temp17 $end
+$var wire 1 I! temp18 $end
+$var wire 1 J! temp19 $end
+$var wire 1 K! temp21 $end
+$var wire 1 L! temp22 $end
+$upscope $end
+
+
+$scope module nsd_unit $end
+$var wire 2 ! pos1 [1:0] $end
+$var wire 2 " pos2 [1:0] $end
+$var wire 2 # pos3 [1:0] $end
+$var wire 2 $ pos4 [1:0] $end
+$var wire 2 % pos5 [1:0] $end
+$var wire 2 & pos6 [1:0] $end
+$var wire 2 ' pos7 [1:0] $end
+$var wire 2 ( pos8 [1:0] $end
+$var wire 2 ) pos9 [1:0] $end
+$var wire 1 [ no_space $end
+$var wire 1 M! temp1 $end
+$var wire 1 N! temp2 $end
+$var wire 1 O! temp3 $end
+$var wire 1 P! temp4 $end
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+$var wire 1 R! temp6 $end
+$var wire 1 S! temp7 $end
+$var wire 1 T! temp8 $end
+$var wire 1 U! temp9 $end
+$upscope $end
+
+
+$scope module tic_tac_toe_controller $end
+$var wire 1 1 clock $end
+$var wire 1 2 reset $end
+$var wire 1 3 play $end
+$var wire 1 4 pc $end
+$var wire 1 W illegal_move $end
+$var wire 1 [ no_space $end
+$var wire 1 X win $end
+$var reg 1 V! computer_play $end
+$var reg 1 W! player_play $end
+$var reg 2 X! current_state [1:0] $end
+$var reg 2 Y! next_state [1:0] $end
+$var parameter 2 Z! IDLE [1:0] $end
+$var parameter 2 [! PLAYER [1:0] $end
+$var parameter 2 \! COMPUTER [1:0] $end
+$var parameter 2 ]! GAME_DONE [1:0] $end
+$upscope $end
+
+$upscope $end
+
+$upscope $end
+
+$enddefinitions $end
+$dumpvars
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test-vcd-files/sources.csv

@@ -0,0 +1,4 @@
+Icarus,Verilator,GHDL,VCS,QuestaSim,ModelSim,Quartus,SystemC,Treadle,Aldec,Riviera-PRO,MyHDL,ncsim,xilinx_isim,vivado,GTKWave-Analyzer
+https://github.com/dpretet/vcd/blob/master/test1.vcd,https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd,https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd,https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd,https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd,https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd,https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd,https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd,https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd,https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd,https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd,https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd,https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd,https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd,https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd,https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd
+https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd,https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd,https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd,https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd,https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd,https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd,,https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd,,,,https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd,,https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd,https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd,
+https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd,,https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd,https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd,,,,,,,,https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd,,https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd,,

test-vcd-files/treadle/GCD.vcd

@@ -0,0 +1,79 @@
+
+$date
+  2016-10-13T16:31+0000
+$end
+$version
+  0.1
+$end
+$comment
+  
+$end
+$timescale 1ps  $end
+$scope module GCD $end
+$var wire 32 . GEN_0 $end
+$var wire 32 + GEN_1 $end
+$var wire 1 ) T_13 $end
+$var wire 33 , T_14 $end
+$var wire 32 - T_15 $end
+$var wire 1 * T_17 $end
+$var wire 33 / T_18 $end
+$var wire 32 0 T_19 $end
+$var wire 1 % T_21 $end
+$var wire 32 ! io_a $end
+$var wire 32 " io_b $end
+$var wire 1 # io_e $end
+$var wire 1 & io_v $end
+$var wire 32 ( io_z $end
+$var wire 32 ' x $end
+$var wire 32 $ y $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +
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test-vcd-files/vcs/Apb_slave_uvm_new.vcd

@@ -0,0 +1,430 @@
+$date
+	Mon May 24 02:40:52 2021
+$end
+
+$version
+	Synopsys VCS version Q-2020.03-SP1-1
+$end
+
+$timescale
+	1ns
+$end
+
+$comment Csum: 1 5fb93f7337e7c1f7 $end
+
+
+$scope module $unit $end
+$upscope $end
+
+
+$scope module apb_pkg $end
+$upscope $end
+
+
+$scope module top $end
+$var reg 1 ! clk $end
+
+$scope begin unnamed$$_vcs_2 $end
+$upscope $end
+
+
+$scope begin unnamed$$_vcs_0 $end
+$upscope $end
+
+
+$scope begin unnamed$$_vcs_1 $end
+$upscope $end
+
+
+$scope begin unnamed$$_vcs_3 $end
+$upscope $end
+
+
+$scope module masslav_if $end
+$var reg 1 " clk $end
+$var reg 32 # Paddr [31:0] $end
+$var reg 32 $ Pwdata [31:0] $end
+$var reg 1 % Psel $end
+$var reg 1 & Pwrite $end
+$var reg 1 ' Penable $end
+$var reg 1 ( Pready $end
+$var reg 32 ) Prdata [31:0] $end
+$var reg 1 * Pslave_err $end
+$upscope $end
+
+$upscope $end
+
+
+$scope module uvm_pkg $end
+$var reg 32 + UVM_UNBOUNDED_CONNECTIONS [31:0] $end
+$var reg 1 , uvm_start_uvm_declarations $end
+$var time 64 - setting_offset $end
+$var reg 32 . setting_verbosity [31:0] $end
+$var reg 1 / is_verdi_set_verbosity_called $end
+$var reg 32 0 uvm_global_random_seed [31:0] $end
+$var reg 1 1 is_uvm_factory_trace_checked $end
+$var reg 1 2 is_verdi_trace_fac $end
+$upscope $end
+
+$enddefinitions $end
+
+#0
+$dumpvars
+11
+0/
+02
+1,
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