notable restructuring

tests/vcd-files/quartus/wave_registradores.vcd

@@ -0,0 +1,151 @@
+$date
+     Dec 16, 2020       19:50:58
+$end
+
+$version
+ SystemC 2.3.3-Accellera --- Nov 12 2020 19:12:35
+$end
+
+$timescale
+     1 ps
+$end
+
+$scope module SystemC $end
+$var wire    1  aaaaa  clock       $end
+$var wire    1  aaaab  mi_RegWrite       $end
+$var wire    5  aaaac  i_ReadRegister1 [4:0]  $end
+$var wire    5  aaaad  i_ReadRegister2 [4:0]  $end
+$var wire    5  aaaae  i_WriteRegister [4:0]  $end
+$var wire   32  aaaaf  i_WriteData [31:0]  $end
+$var wire   32  aaaag  o_ReadData1 [31:0]  $end
+$var wire   32  aaaah  o_ReadData2 [31:0]  $end
+$upscope $end
+$enddefinitions  $end
+
+$comment
+All initial values are dumped below at time 0 sec = 0 timescale units.
+$end
+
+$dumpvars
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+$end
+
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