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notable restructuring

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This commit is contained in:
Yehowshua Immanuel 2022-09-09 02:59:33 -04:00
parent 4c1af97760
commit 320b0d348d
43 changed files with 154 additions and 142 deletions
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3
src/lib.rs
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@ -1 +1,2 @@
pub mod vcd;
mod vcd;
pub use vcd::*;

66
src/main.rs
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@ -1,66 +0,0 @@
use clap::Parser;
use std::fs::File;
pub mod test;
pub mod vcd;
use vcd::*;
use num::{BigUint};
#[derive(Parser)]
struct Cli {
/// The path to the file to read
#[clap(parse(from_os_str))]
path: std::path::PathBuf,
}
fn main() -> std::io::Result<()> {
let args = Cli::parse();
use std::time::Instant;
let now = Instant::now();
let file = File::open(&args.path)?;
let vcd = parse_vcd(file).unwrap();
let elapsed = now.elapsed();
println!("Parsed VCD file {} : {:.2?}", &args.path.as_os_str().to_str().unwrap(), elapsed);
// the following is really only for test-vcd-files/icarus/CPU.vcd
// at the moment
if args.path.as_os_str().to_str().unwrap() == "test-vcd-files/icarus/CPU.vcd" {
let rs2_data_signal = &vcd.all_signals[51];
let name = rs2_data_signal.name();
// query testbench -> CPU -> rs2_data[31:0] @ 4687s
let time = BigUint::from(4687u32);
let val = rs2_data_signal
.query_num_val_on_tmln(
&time,
&vcd.tmstmps_encoded_as_u8s,
&vcd.all_signals,
)
.unwrap();
println!("Signal `{name}` has value `{val}` at time `{time}`");
// also need to test testbench -> CPU -> ID_EX_RD[4:0]
}
// this is to help with testing stringed enums
if args.path.as_os_str().to_str().unwrap() == "test-vcd-files/amaranth/up_counter.vcd" {
let state_signal = &vcd.all_signals[4];
let name = state_signal.name();
let time = BigUint::from(57760000u32);
let val = state_signal
.query_string_val_on_tmln(
&time,
&vcd.tmstmps_encoded_as_u8s,
&vcd.all_signals,
)
.unwrap();
println!("Signal `{name}` has value `{val}` at time `{time}`");
}
Ok(())
}

2
src/test.rs
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@ -1,2 +0,0 @@
mod files;
pub use files::*;

71
src/test/files.rs
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@ -1,71 +0,0 @@
// TODO: we should eventually be able to only test on just
// the files const
pub const FILES : [&str; 30] = [
"./test-vcd-files/aldec/SPI_Write.vcd",
"./test-vcd-files/ghdl/alu.vcd",
"./test-vcd-files/ghdl/idea.vcd",
"./test-vcd-files/ghdl/pcpu.vcd",
"./test-vcd-files/gtkwave-analyzer/perm_current.vcd",
"./test-vcd-files/icarus/CPU.vcd",
"./test-vcd-files/icarus/rv32_soc_TB.vcd",
"./test-vcd-files/icarus/test1.vcd",
"./test-vcd-files/model-sim/CPU_Design.msim.vcd",
"./test-vcd-files/model-sim/clkdiv2n_tb.vcd",
"./test-vcd-files/my-hdl/Simple_Memory.vcd",
"./test-vcd-files/my-hdl/sigmoid_tb.vcd",
"./test-vcd-files/my-hdl/top.vcd",
"./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
"./test-vcd-files/quartus/mipsHardware.vcd",
"./test-vcd-files/quartus/wave_registradores.vcd",
"./test-vcd-files/questa-sim/dump.vcd",
"./test-vcd-files/questa-sim/test.vcd",
"./test-vcd-files/riviera-pro/dump.vcd",
"./test-vcd-files/systemc/waveform.vcd",
"./test-vcd-files/treadle/GCD.vcd",
"./test-vcd-files/vcs/Apb_slave_uvm_new.vcd",
"./test-vcd-files/vcs/datapath_log.vcd",
"./test-vcd-files/vcs/processor.vcd",
"./test-vcd-files/verilator/swerv1.vcd",
"./test-vcd-files/verilator/vlt_dump.vcd",
"./test-vcd-files/vivado/iladata.vcd",
"./test-vcd-files/xilinx_isim/test.vcd",
"./test-vcd-files/xilinx_isim/test1.vcd",
// TODO : add signal ignore list to handle bitwidth mismatches
"./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
];
pub const GOOD_DATE_FILES : [&str; 24] = [
"./test-vcd-files/aldec/SPI_Write.vcd",
"./test-vcd-files/ghdl/alu.vcd",
"./test-vcd-files/ghdl/idea.vcd",
"./test-vcd-files/ghdl/pcpu.vcd",
"./test-vcd-files/gtkwave-analyzer/perm_current.vcd",
"./test-vcd-files/icarus/CPU.vcd",
"./test-vcd-files/icarus/rv32_soc_TB.vcd",
"./test-vcd-files/icarus/test1.vcd",
"./test-vcd-files/model-sim/CPU_Design.msim.vcd",
"./test-vcd-files/model-sim/clkdiv2n_tb.vcd",
"./test-vcd-files/my-hdl/Simple_Memory.vcd",
"./test-vcd-files/my-hdl/sigmoid_tb.vcd",
"./test-vcd-files/my-hdl/top.vcd",
"./test-vcd-files/questa-sim/dump.vcd",
"./test-vcd-files/questa-sim/test.vcd",
"./test-vcd-files/riviera-pro/dump.vcd",
"./test-vcd-files/vcs/Apb_slave_uvm_new.vcd",
"./test-vcd-files/vcs/datapath_log.vcd",
"./test-vcd-files/vcs/processor.vcd",
"./test-vcd-files/verilator/swerv1.vcd",
"./test-vcd-files/verilator/vlt_dump.vcd",
"./test-vcd-files/xilinx_isim/test.vcd",
"./test-vcd-files/xilinx_isim/test1.vcd",
"./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
];
pub const BAD_DATE_FILES : [&str; 6] = [
"./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
"./test-vcd-files/quartus/mipsHardware.vcd",
"./test-vcd-files/quartus/wave_registradores.vcd",
"./test-vcd-files/systemc/waveform.vcd",
"./test-vcd-files/treadle/GCD.vcd",
"./test-vcd-files/vivado/iladata.vcd",
];

42
src/vcd/parse.rs
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@ -41,44 +41,4 @@ pub fn parse_vcd(file: File) -> Result<VCD, String> {
parse_events(&mut word_gen, &mut vcd, &mut signal_map)?;
Ok(vcd)
}
#[cfg(test)]
mod tests {
use super::*;
use crate::test;
use std::fs::File;
#[test]
fn headers() {
// TODO: eventually, once all dates pass, merge the following
// two loops
// testing dates
for file in test::GOOD_DATE_FILES {
let metadata = parse_metadata(&mut WordReader::new(File::open(file).unwrap()));
assert!(metadata.is_ok());
assert!(metadata.unwrap().date.is_some());
}
for file in test::FILES {
let metadata = parse_metadata(&mut WordReader::new(File::open(file).unwrap()));
assert!(metadata.is_ok());
let (scalar, _timescale) = metadata.unwrap().timescale;
assert!(scalar.is_some());
}
}
#[test]
fn scopes() {
// see if we can parse all signal trees successfully
for file_name in test::FILES {
let file = File::open(file_name).unwrap();
let vcd = parse_vcd(file);
if !vcd.is_ok() {
dbg!(file_name);
vcd.unwrap();
}
}
}
}
}