From 29d72b6e9c470f1427accc9c5893923cdc5ee65c Mon Sep 17 00:00:00 2001
From: Yehowshua Immanuel <yehowshua@theperfect.computer>
Date: Fri, 24 Jun 2022 22:22:55 -0400
Subject: [PATCH] postpone adding date support for ncsim, quartus, treadle, and
 vivado

---
 src/test/files.rs                 | 52 ++++++++++++++++++++++++++-----
 src/vcd/parse.rs                  | 18 ++++++++++-
 src/vcd/parse/combinator_atoms.rs | 14 +++++++++
 3 files changed, 76 insertions(+), 8 deletions(-)

diff --git a/src/test/files.rs b/src/test/files.rs
index e658a97..4cea310 100644
--- a/src/test/files.rs
+++ b/src/test/files.rs
@@ -1,4 +1,6 @@
-pub const files : [&str; 24] = [
+// TODO: we should eventually be able to only test on just
+// the files const
+pub const files : [&str; 30] = [
     "./test-vcd-files/aldec/SPI_Write.vcd",
     "./test-vcd-files/ghdl/alu.vcd",
     "./test-vcd-files/ghdl/idea.vcd",
@@ -12,21 +14,57 @@ pub const files : [&str; 24] = [
     "./test-vcd-files/my-hdl/Simple_Memory.vcd",
     "./test-vcd-files/my-hdl/sigmoid_tb.vcd",
     "./test-vcd-files/my-hdl/top.vcd",
-    // "./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
-    // "./test-vcd-files/quartus/mipsHardware.vcd",
-    // "./test-vcd-files/quartus/wave_registradores.vcd",
+    "./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
+    "./test-vcd-files/quartus/mipsHardware.vcd",
+    "./test-vcd-files/quartus/wave_registradores.vcd",
     "./test-vcd-files/questa-sim/dump.vcd",
     "./test-vcd-files/questa-sim/test.vcd",
     "./test-vcd-files/riviera-pro/dump.vcd",
-    // "./test-vcd-files/systemc/waveform.vcd",
-    // "./test-vcd-files/treadle/GCD.vcd",
+    "./test-vcd-files/systemc/waveform.vcd",
+    "./test-vcd-files/treadle/GCD.vcd",
     "./test-vcd-files/vcs/Apb_slave_uvm_new.vcd",
     "./test-vcd-files/vcs/datapath_log.vcd",
     "./test-vcd-files/vcs/processor.vcd",
     "./test-vcd-files/verilator/swerv1.vcd",
     "./test-vcd-files/verilator/vlt_dump.vcd",
-    // "./test-vcd-files/vivado/iladata.vcd",
+    "./test-vcd-files/vivado/iladata.vcd",
     "./test-vcd-files/xilinx_isim/test.vcd",
     "./test-vcd-files/xilinx_isim/test1.vcd",
     "./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
+];
+
+pub const good_date_files : [&str; 24] = [
+    "./test-vcd-files/aldec/SPI_Write.vcd",
+    "./test-vcd-files/ghdl/alu.vcd",
+    "./test-vcd-files/ghdl/idea.vcd",
+    "./test-vcd-files/ghdl/pcpu.vcd",
+    "./test-vcd-files/gtkwave-analyzer/perm_current.vcd",
+    "./test-vcd-files/icarus/CPU.vcd",
+    "./test-vcd-files/icarus/rv32_soc_TB.vcd",
+    "./test-vcd-files/icarus/test1.vcd",
+    "./test-vcd-files/model-sim/CPU_Design.msim.vcd",
+    "./test-vcd-files/model-sim/clkdiv2n_tb.vcd",
+    "./test-vcd-files/my-hdl/Simple_Memory.vcd",
+    "./test-vcd-files/my-hdl/sigmoid_tb.vcd",
+    "./test-vcd-files/my-hdl/top.vcd",
+    "./test-vcd-files/questa-sim/dump.vcd",
+    "./test-vcd-files/questa-sim/test.vcd",
+    "./test-vcd-files/riviera-pro/dump.vcd",
+    "./test-vcd-files/vcs/Apb_slave_uvm_new.vcd",
+    "./test-vcd-files/vcs/datapath_log.vcd",
+    "./test-vcd-files/vcs/processor.vcd",
+    "./test-vcd-files/verilator/swerv1.vcd",
+    "./test-vcd-files/verilator/vlt_dump.vcd",
+    "./test-vcd-files/xilinx_isim/test.vcd",
+    "./test-vcd-files/xilinx_isim/test1.vcd",
+    "./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd"
+];
+
+pub const bad_date_files : [&str; 6] = [
+    "./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd",
+    "./test-vcd-files/quartus/mipsHardware.vcd",
+    "./test-vcd-files/quartus/wave_registradores.vcd",
+    "./test-vcd-files/systemc/waveform.vcd",
+    "./test-vcd-files/treadle/GCD.vcd",
+    "./test-vcd-files/vivado/iladata.vcd",
 ];
\ No newline at end of file
diff --git a/src/vcd/parse.rs b/src/vcd/parse.rs
index 816f22a..5fc9a69 100644
--- a/src/vcd/parse.rs
+++ b/src/vcd/parse.rs
@@ -29,7 +29,10 @@ mod tests {
     use std::fs::File;
     #[test]
     fn headers() {
-        for file in test::files {
+        // TODO: eventually, once all dates pass, merge the following
+        // two loops
+        // testing dates
+        for file in test::good_date_files {
             let metadata = parse_metadata(
                 &mut WordReader::new(
                     File::open(file)
@@ -40,5 +43,18 @@ mod tests {
             assert!(metadata.unwrap().date.is_some());
         }
 
+        for file in test::files {
+            let metadata = parse_metadata(
+                &mut WordReader::new(
+                    File::open(file)
+                    .unwrap()
+                )
+            );
+            assert!(metadata.is_ok());
+
+            let (scalar, timescale) = metadata.unwrap().timescale;
+            assert!(scalar.is_some());
+        }
+
     }
 }
\ No newline at end of file
diff --git a/src/vcd/parse/combinator_atoms.rs b/src/vcd/parse/combinator_atoms.rs
index 86ca84a..0627d3e 100644
--- a/src/vcd/parse/combinator_atoms.rs
+++ b/src/vcd/parse/combinator_atoms.rs
@@ -29,6 +29,20 @@ pub(super) fn take_until<'a>(word : &'a str, pattern : u8) -> ParseResult<'a> {
 
 }
 
+// TODO: if I end up using simulator specific date parsers, ``take_until`` may
+// suffice rendering this function obselete, at which point I should delete it.
+pub(super) fn truncate_last_chr_when<'a>(word : &'a str, cond : fn(u8) -> bool) -> &'a str {
+    let last_chr = word.as_bytes().last().unwrap();
+    let mut new_end_index = word.len();
+
+    if cond(*last_chr) {
+        new_end_index -= 1;
+    }
+    
+    return &word[0..new_end_index]
+
+}
+
 pub(super) fn take_while<'a>(word : &'a str, cond : fn(u8) -> bool) -> ParseResult<'a> {
     let mut new_start  = 0;