From 21661d7967177a8011c5eee5be36fbb6d5702adc Mon Sep 17 00:00:00 2001
From: Void User <void@power9.hsd1.ga.comcast.net>
Date: Thu, 23 Jun 2022 20:56:44 -0400
Subject: [PATCH] no longer need a list of files in the REAMDE

---
 README.md | 36 ++----------------------------------
 1 file changed, 2 insertions(+), 34 deletions(-)

diff --git a/README.md b/README.md
index d8b45c1..750c0a2 100644
--- a/README.md
+++ b/README.md
@@ -36,8 +36,8 @@ You can run all the tests with ``cargo test``
  - [x] make parse/types.rs
  - [x] remove/replace calls to match_not_empty
  - [x] Split ``parse.rs``. It's getting too large.
+ - [x] move list of files to separate test file/folder
  - [ ] support parsing dates with commas
- - [ ] move list of files to separate test file/folder
  - [ ] Fix warning especially usage and restriction warnings once I'm
        able to successfully parse all sample VCDs.
 
@@ -50,36 +50,4 @@ You can run all the tests with ``cargo test``
  - [ ] Send survey to community channel.
 
 # Probably No Longer Needed
- - [ ] Should insert nodes in BFS order
-
-# Files
- - ./test-vcd-files/aldec/SPI_Write.vcd
- - ./test-vcd-files/ghdl/alu.vcd
- - ./test-vcd-files/ghdl/idea.vcd
- - ./test-vcd-files/ghdl/pcpu.vcd
- - ./test-vcd-files/gtkwave-analyzer/perm_current.vcd
- - ./test-vcd-files/icarus/CPU.vcd
- - ./test-vcd-files/icarus/rv32_soc_TB.vcd
- - ./test-vcd-files/icarus/test1.vcd
- - ./test-vcd-files/model-sim/CPU_Design.msim.vcd
- - ./test-vcd-files/model-sim/clkdiv2n_tb.vcd
- - ./test-vcd-files/my-hdl/Simple_Memory.vcd
- - ./test-vcd-files/my-hdl/sigmoid_tb.vcd
- - ./test-vcd-files/my-hdl/top.vcd
- - ./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd
- - ./test-vcd-files/quartus/mipsHardware.vcd
- - ./test-vcd-files/quartus/wave_registradores.vcd
- - ./test-vcd-files/questa-sim/dump.vcd
- - ./test-vcd-files/questa-sim/test.vcd
- - ./test-vcd-files/riviera-pro/dump.vcd
- - ./test-vcd-files/systemc/waveform.vcd
- - ./test-vcd-files/treadle/GCD.vcd
- - ./test-vcd-files/vcs/Apb_slave_uvm_new.vcd
- - ./test-vcd-files/vcs/datapath_log.vcd
- - ./test-vcd-files/vcs/processor.vcd
- - ./test-vcd-files/verilator/swerv1.vcd
- - ./test-vcd-files/verilator/vlt_dump.vcd
- - ./test-vcd-files/vivado/iladata.vcd
- - ./test-vcd-files/xilinx_isim/test.vcd
- - ./test-vcd-files/xilinx_isim/test1.vcd
- - ./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd
\ No newline at end of file
+ - [ ] Should insert nodes in BFS order
\ No newline at end of file