FastWaveBackend/tests/vcd-files/vcs/processor.vcd

$date
	Mon Dec  8 11:31:40 2014
$end

$version
	Synopsys VCS version I-2014.03-2
$end

$timescale
	1ps
$end

$comment Csum: 1 d0ee42a2602ee3fe $end


$scope module tb_processor $end
$var reg 1 ! clk $end
$var reg 1 " rst $end
$var wire 8 # addr [7:0] $end
$var wire 1 $ wrt $end
$var wire 1 % rd $end
$var wire 8 & dat [7:0] $end
$var reg 8 ' out_data [7:0] $end

$scope module uut $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 8 # addr [7:0] $end
$var wire 8 & dat [7:0] $end
$var wire 1 $ wrt $end
$var wire 1 % rd $end
$var wire 1 ( ar_on_data $end
$var wire 1 ) data_on_ar $end
$var wire 1 * ar_on_add $end
$var wire 1 + gr_on_data $end
$var wire 1 , lsb_on_gr $end
$var wire 1 - msb_on_gr $end
$var wire 1 . data_on_dr $end
$var wire 1 / dr_on_data $end
$var wire 1 0 load_FR_On_data $end
$var wire 1 1 ALU_cin $end
$var wire 1 2 ALU_sel $end
$var wire 2 3 add_sel_a [1:0] $end
$var wire 2 4 add_sel_b [1:0] $end
$var wire 1 5 alu_2_data $end
$var wire 1 6 ar_on_pr $end
$var wire 1 7 pr_on_data $end
$var wire 1 8 pr_on_add $end
$var wire 1 9 increment_pr $end
$var wire 1 : ir_on_data $end
$var wire 1 ; data_on_ir $end
$var wire 8 < machine_code [7:0] $end

$scope module data_block_instantiation $end
$var wire 8 & data_bus [7:0] $end
$var wire 8 # address_bus [7:0] $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 6 ar_on_pr $end
$var wire 1 7 pr_on_data $end
$var wire 1 8 pr_on_add $end
$var wire 1 9 increment_pr $end
$var wire 1 : ir_on_data $end
$var wire 1 ; data_on_ir $end
$var wire 8 < machine_code [7:0] $end
$var wire 1 ( ar_on_data $end
$var wire 1 ) data_on_ar $end
$var wire 1 * ar_on_add $end
$var wire 1 + gr_on_data $end
$var wire 1 , lsb_on_gr $end
$var wire 1 - msb_on_gr $end
$var wire 1 . data_on_dr $end
$var wire 1 / dr_on_data $end
$var wire 1 0 load_FR_On_data $end
$var wire 1 1 ALU_cin $end
$var wire 1 2 ALU_sel $end
$var wire 1 5 alu_2_data $end
$var wire 2 3 add_sel_a [1:0] $end
$var wire 2 4 add_sel_b [1:0] $end
$var reg 8 = mux_o1 [7:0] $end
$var reg 8 > mux_o2 [7:0] $end
$var wire 8 ? pr_on_bus [7:0] $end
$var wire 8 @ dr_2_bus [7:0] $end
$var wire 8 A gr_2_bus [7:0] $end
$var wire 8 B ar_2_bus [7:0] $end
$var wire 8 C alu_out [7:0] $end
$var wire 8 < ir_2_bus [7:0] $end
$var wire 4 D flag_2_data [3:0] $end
$var wire 1 E Cout $end

$scope begin mux_block1 $end
$upscope $end


$scope begin mux_block2 $end
$upscope $end


$scope module General_register $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 , lsb_on_gr $end
$var wire 1 - msb_on_gr $end
$var wire 8 & bus_2_gr [7:0] $end
$var reg 8 F gr_2_bus [7:0] $end
$upscope $end


$scope module Program_counter $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 6 ar_on_pr $end
$var wire 1 9 increment_pr $end
$var wire 8 & data_2_pr [7:0] $end
$var reg 8 G pr_on_bus [7:0] $end
$upscope $end


$scope module Address_register $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 ) data_on_ar $end
$var wire 8 & data_2_ar [7:0] $end
$var reg 8 H ar_2_bus [7:0] $end
$upscope $end


$scope module Data_register $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 . data_on_dr $end
$var wire 8 & bus_2_dr [7:0] $end
$var reg 8 I dr_2_bus [7:0] $end
$upscope $end


$scope module Instruction_register $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 ; data_on_ir $end
$var wire 8 & data_2_ir [7:0] $end
$var reg 8 J ir_2_bus [7:0] $end
$upscope $end


$scope module new_alu $end
$var wire 1 K a1 [7] $end
$var wire 1 L a1 [6] $end
$var wire 1 M a1 [5] $end
$var wire 1 N a1 [4] $end
$var wire 1 O a1 [3] $end
$var wire 1 P a1 [2] $end
$var wire 1 Q a1 [1] $end
$var wire 1 R a1 [0] $end
$var wire 1 S b1 [7] $end
$var wire 1 T b1 [6] $end
$var wire 1 U b1 [5] $end
$var wire 1 V b1 [4] $end
$var wire 1 W b1 [3] $end
$var wire 1 X b1 [2] $end
$var wire 1 Y b1 [1] $end
$var wire 1 Z b1 [0] $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 1 ALU_cin1 $end
$var wire 1 2 ALU_sel1 $end
$var wire 8 C alu_out [7:0] $end
$var wire 1 E Cout $end
$var wire 1 [ c0 $end
$var wire 1 \ c1 $end
$var wire 1 ] c2 $end
$var wire 1 ^ c3 $end
$var wire 1 _ c4 $end
$var wire 1 ` c5 $end
$var wire 1 a c6 $end
$var wire 1 b C0 $end
$var wire 1 c C1 $end
$var wire 1 d C2 $end
$var wire 1 e C3 $end
$var wire 1 f C4 $end
$var wire 1 g C5 $end
$var wire 1 h C6 $end

$scope module f1 $end
$var wire 1 1 cin $end
$var wire 1 R inp1 $end
$var wire 1 Z inp2 $end
$var wire 1 2 sel $end
$var wire 1 i sum $end
$var wire 1 b cout $end
$var wire 1 j w1 $end
$var wire 1 k w2 $end
$var wire 1 l w3 $end
$var wire 1 m w0 $end
$upscope $end


$scope module f2 $end
$var wire 1 b cin $end
$var wire 1 Q inp1 $end
$var wire 1 Y inp2 $end
$var wire 1 2 sel $end
$var wire 1 n sum $end
$var wire 1 c cout $end
$var wire 1 o w1 $end
$var wire 1 p w2 $end
$var wire 1 q w3 $end
$var wire 1 r w0 $end
$upscope $end


$scope module f3 $end
$var wire 1 c cin $end
$var wire 1 P inp1 $end
$var wire 1 X inp2 $end
$var wire 1 2 sel $end
$var wire 1 s sum $end
$var wire 1 d cout $end
$var wire 1 t w1 $end
$var wire 1 u w2 $end
$var wire 1 v w3 $end
$var wire 1 w w0 $end
$upscope $end


$scope module f4 $end
$var wire 1 d cin $end
$var wire 1 O inp1 $end
$var wire 1 W inp2 $end
$var wire 1 2 sel $end
$var wire 1 x sum $end
$var wire 1 e cout $end
$var wire 1 y w1 $end
$var wire 1 z w2 $end
$var wire 1 { w3 $end
$var wire 1 | w0 $end
$upscope $end


$scope module f5 $end
$var wire 1 e cin $end
$var wire 1 N inp1 $end
$var wire 1 V inp2 $end
$var wire 1 2 sel $end
$var wire 1 } sum $end
$var wire 1 f cout $end
$var wire 1 ~ w1 $end
$var wire 1 "! w2 $end
$var wire 1 "" w3 $end
$var wire 1 "# w0 $end
$upscope $end


$scope module f6 $end
$var wire 1 f cin $end
$var wire 1 M inp1 $end
$var wire 1 U inp2 $end
$var wire 1 2 sel $end
$var wire 1 "$ sum $end
$var wire 1 g cout $end
$var wire 1 "% w1 $end
$var wire 1 "& w2 $end
$var wire 1 "' w3 $end
$var wire 1 "( w0 $end
$upscope $end


$scope module f7 $end
$var wire 1 g cin $end
$var wire 1 L inp1 $end
$var wire 1 T inp2 $end
$var wire 1 2 sel $end
$var wire 1 ") sum $end
$var wire 1 h cout $end
$var wire 1 "* w1 $end
$var wire 1 "+ w2 $end
$var wire 1 ", w3 $end
$var wire 1 "- w0 $end
$upscope $end


$scope module f8 $end
$var wire 1 h cin $end
$var wire 1 K inp1 $end
$var wire 1 S inp2 $end
$var wire 1 2 sel $end
$var wire 1 ". sum $end
$var wire 1 E cout $end
$var wire 1 "/ w1 $end
$var wire 1 "0 w2 $end
$var wire 1 "1 w3 $end
$var wire 1 "2 w0 $end
$upscope $end

$upscope $end


$scope module Flag_register $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 5 alu_2_data $end
$var wire 1 E alu_cout $end
$var wire 8 C alu_output [7:0] $end
$var reg 4 "3 flag_reg [3:0] $end
$upscope $end

$upscope $end


$scope module controller_instant $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var reg 1 "4 rd_mem $end
$var reg 1 "5 wr_mem $end
$var reg 1 "6 crt_ar_on_pr $end
$var reg 1 "7 crt_pr_on_data $end
$var reg 1 "8 crt_pr_on_add $end
$var reg 1 "9 crt_increment_pr $end
$var reg 1 ": crt_ir_on_data $end
$var reg 1 "; crt_data_on_ir $end
$var wire 8 < crt_machine_code [7:0] $end
$var reg 1 "< crt_ar_on_data $end
$var reg 1 "= crt_data_on_ar $end
$var reg 1 "> crt_ar_on_add $end
$var reg 1 "? crt_gr_on_data $end
$var reg 1 "@ crt_lsb_on_gr $end
$var reg 1 "A crt_msb_on_gr $end
$var reg 1 "B crt_data_on_dr $end
$var reg 1 "C crt_dr_on_data $end
$var reg 1 "D crt_load_FR_On_data $end
$var reg 1 "E crt_alu_2_data $end
$var reg 1 "F crt_ALU_cin $end
$var reg 1 "G crt_ALU_sel $end
$var reg 2 "H crt_add_sel_a [1:0] $end
$var reg 2 "I crt_add_sel_b [1:0] $end
$var reg 2 "J present_state [1:0] $end
$var reg 2 "K next_state [1:0] $end
$upscope $end

$upscope $end

$upscope $end

$enddefinitions $end

#0
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$end
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