FastWaveBackend/tests/vcd-files/quartus/mipsHardware.vcd

$comment
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
$end

$date 
  10/19/2019 09:49:22 
$end
$version 
 QUARTUS_VCD_EXPORT 1.0 
$end
$timescale
  1 ps
$end
$scope module schemeHard $end
$var reg 7 ! stateOut[6:0] $end
$var reg 1 " clk $end
$var reg 32 # aluAOut[31:0] $end
$var reg 32 $ aluBOut[31:0] $end
$var reg 3 % alucontrol[2:0] $end
$var reg 32 & aluresult[31:0] $end
$var reg 16 ' bSExtended[15:0] $end
$var reg 2 ( controlLS[1:0] $end
$var reg 1 ) debug $end
$var reg 1 * divByzeroOUT $end
$var reg 1 + divSTOPOUT $end
$var reg 32 , epcOUT[31:0] $end
$var reg 6 - funct[5:0] $end
$var reg 6 . functOut[5:0] $end
$var reg 32 / hiOut[31:0] $end
$var reg 1 0 instControl $end
$var reg 32 1 IORDout[31:0] $end
$var reg 32 2 j[31:0] $end
$var reg 32 3 loOut[31:0] $end
$var reg 32 4 LuiOut[31:0] $end
$var reg 32 5 MDROut[31:0] $end
$var reg 32 6 memoriaOut[31:0] $end
$var reg 4 7 memtoRegmux[3:0] $end
$var reg 1 8 multStopOut $end
$var reg 1 9 muxXCHG $end
$var reg 6 : opcodeW[5:0] $end
$var reg 1 ; overflow $end
$var reg 32 < pcOut[31:0] $end
$var reg 1 = pcWriteS $end
$var reg 32 > pcWriteSource[31:0] $end
$var reg 5 ? rd[4:0] $end
$var reg 16 @ rdshf[15:0] $end
$var reg 1 A RegWriteC $end
$var reg 1 B reset $end
$var reg 1 C resetD2 $end
$var reg 5 D rs[4:0] $end
$var reg 5 E rt[4:0] $end
$var reg 32 F sExtended[31:0] $end
$var reg 5 G shift[4:0] $end
$var reg 32 H shiftOut[31:0] $end
$var reg 1 I sltOut $end
$var reg 32 J SourceSh[31:0] $end
$var reg 32 K storeB[31:0] $end
$var reg 32 L storeData[31:0] $end
$var reg 32 M storeOUT[31:0] $end
$var reg 1 N storeWr $end
$var reg 32 O tratamento[31:0] $end
$var reg 32 P ulaOut_t[31:0] $end
$var reg 32 Q wrData[31:0] $end
$var reg 5 R wrReg[4:0] $end
$var reg 32 S xCHG[31:0] $end
$var reg 32 T xchgOUT[31:0] $end
$scope module inst6 $end
$var reg 32 U Reg0[31:0] $end
$var reg 32 V Reg1[31:0] $end
$var reg 32 W Reg2[31:0] $end
$var reg 32 X Reg3[31:0] $end
$var reg 32 Y Reg4[31:0] $end
$var reg 32 Z Reg5[31:0] $end
$var reg 32 [ Reg6[31:0] $end
$var reg 32 \ Reg7[31:0] $end
$var reg 32 ] Reg8[31:0] $end
$var reg 32 ^ Reg9[31:0] $end
$var reg 32 _ Reg10[31:0] $end
$var reg 32 ` Reg11[31:0] $end
$var reg 32 a Reg12[31:0] $end
$var reg 32 b Reg13[31:0] $end
$var reg 32 c Reg14[31:0] $end
$var reg 32 d Reg15[31:0] $end
$var reg 32 e Reg16[31:0] $end
$var reg 32 f Reg17[31:0] $end
$var reg 32 g Reg18[31:0] $end
$var reg 32 h Reg19[31:0] $end
$var reg 32 i Reg20[31:0] $end
$var reg 32 j Reg21[31:0] $end
$var reg 32 k Reg22[31:0] $end
$var reg 32 l Reg23[31:0] $end
$var reg 32 m Reg24[31:0] $end
$var reg 32 n Reg25[31:0] $end
$var reg 32 o Reg26[31:0] $end
$var reg 32 p Reg27[31:0] $end
$var reg 32 q Reg28[31:0] $end
$var reg 32 r Reg29[31:0] $end
$var reg 32 s Reg30[31:0] $end
$var reg 32 t Reg31[31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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