FastWaveBackend/tests/vcd-files/my-hdl/top.vcd

$date
    Sun Jun  6 19:30:28 2021
$end
$version
    MyHDL 0.11
$end
$timescale
    1ns
$end

$scope module top $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$scope module clock0 $end
$var reg 1 ! clk $end
$upscope $end
$scope module cpu_top0 $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$var reg 32 # pc $end
$var reg 32 $ pc_next $end
$var reg 32 % jmp_addr $end
$var reg 32 & read_addr $end
$var reg 32 ' instruction $end
$var reg 5 ( ra $end
$var reg 5 ) rb $end
$var reg 5 * wa $end
$var reg 32 + wda $end
$var reg 32 , rda $end
$var reg 32 - rdb $end
$var reg 32 . rdx $end
$var reg 1 / brnch $end
$var reg 1 0 mem_rd $end
$var reg 1 1 mem_to_rgs $end
$var reg 1 2 mem_wr $end
$var reg 1 3 alu_src $end
$var reg 1 4 reg_wr $end
$var reg 64 5 ifid_reg $end
$var reg 4 6 alu_decode $end
$var reg 1 7 pc_sel $end
$var reg 7 8 opcode $end
$var reg 4 9 alu_op $end
$var reg 32 : im_gen $end
$var reg 20 ; padz $end
$var reg 20 < padx $end
$var reg 32 = result $end
$var reg 32 > read_data $end
$var reg 32 ? shl $end
$var reg 153 @ idex_reg $end
$scope module pc_adder $end
$var reg 1 ! clk $end
$var reg 32 # pc $end
$var reg 32 $ pc_next $end
$var reg 1 " reset $end
$upscope $end
$scope module pc_mux $end
$var reg 32 % jmp_addr $end
$var reg 32 # pc $end
$var reg 32 $ pc_next $end
$var reg 1 7 pc_sel $end
$var reg 1 " reset $end
$upscope $end
$scope module pc_assign $end
$var reg 32 # pc $end
$var reg 32 & read_addr $end
$var reg 1 " reset $end
$upscope $end
$scope module inst_mem $end
$var reg 32 ' instruction $end
$var reg 32 & read_addr $end
$var reg 1 " reset $end
$scope module inst_ram $end
$var reg 32 A inst_ram(0) $end
$var reg 32 B inst_ram(1) $end
$var reg 32 C inst_ram(2) $end
$var reg 32 D inst_ram(3) $end
$var reg 32 E inst_ram(4) $end
$var reg 32 F inst_ram(5) $end
$var reg 32 G inst_ram(6) $end
$var reg 32 H inst_ram(7) $end
$var reg 32 I inst_ram(8) $end
$var reg 32 J inst_ram(9) $end
$var reg 32 K inst_ram(10) $end
$var reg 32 L inst_ram(11) $end
$var reg 32 M inst_ram(12) $end
$var reg 32 N inst_ram(13) $end
$var reg 32 O inst_ram(14) $end
$var reg 32 P inst_ram(15) $end
$var reg 32 Q inst_ram(16) $end
$var reg 32 R inst_ram(17) $end
$var reg 32 S inst_ram(18) $end
$var reg 32 T inst_ram(19) $end
$var reg 32 U inst_ram(20) $end
$var reg 32 V inst_ram(21) $end
$var reg 32 W inst_ram(22) $end
$var reg 32 X inst_ram(23) $end
$var reg 32 Y inst_ram(24) $end
$var reg 32 Z inst_ram(25) $end
$var reg 32 [ inst_ram(26) $end
$var reg 32 \ inst_ram(27) $end
$var reg 32 ] inst_ram(28) $end
$var reg 32 ^ inst_ram(29) $end
$var reg 32 _ inst_ram(30) $end
$var reg 32 ` inst_ram(31) $end
$var reg 32 a inst_ram(32) $end
$var reg 32 b inst_ram(33) $end
$var reg 32 c inst_ram(34) $end
$var reg 32 d inst_ram(35) $end
$var reg 32 e inst_ram(36) $end
$var reg 32 f inst_ram(37) $end
$var reg 32 g inst_ram(38) $end
$var reg 32 h inst_ram(39) $end
$var reg 32 i inst_ram(40) $end
$var reg 32 j inst_ram(41) $end
$var reg 32 k inst_ram(42) $end
$var reg 32 l inst_ram(43) $end
$var reg 32 m inst_ram(44) $end
$var reg 32 n inst_ram(45) $end
$var reg 32 o inst_ram(46) $end
$var reg 32 p inst_ram(47) $end
$var reg 32 q inst_ram(48) $end
$var reg 32 r inst_ram(49) $end
$var reg 32 s inst_ram(50) $end
$var reg 32 t inst_ram(51) $end
$var reg 32 u inst_ram(52) $end
$var reg 32 v inst_ram(53) $end
$var reg 32 w inst_ram(54) $end
$var reg 32 x inst_ram(55) $end
$var reg 32 y inst_ram(56) $end
$var reg 32 z inst_ram(57) $end
$var reg 32 { inst_ram(58) $end
$var reg 32 | inst_ram(59) $end
$var reg 32 } inst_ram(60) $end
$var reg 32 ~ inst_ram(61) $end
$var reg 32 "! inst_ram(62) $end
$var reg 32 "" inst_ram(63) $end
$var reg 32 "# inst_ram(64) $end
$var reg 32 "$ inst_ram(65) $end
$var reg 32 "% inst_ram(66) $end
$var reg 32 "& inst_ram(67) $end
$var reg 32 "' inst_ram(68) $end
$var reg 32 "( inst_ram(69) $end
$var reg 32 ") inst_ram(70) $end
$var reg 32 "* inst_ram(71) $end
$var reg 32 "+ inst_ram(72) $end
$var reg 32 ", inst_ram(73) $end
$var reg 32 "- inst_ram(74) $end
$var reg 32 ". inst_ram(75) $end
$var reg 32 "/ inst_ram(76) $end
$var reg 32 "0 inst_ram(77) $end
$var reg 32 "1 inst_ram(78) $end
$var reg 32 "2 inst_ram(79) $end
$var reg 32 "3 inst_ram(80) $end
$var reg 32 "4 inst_ram(81) $end
$var reg 32 "5 inst_ram(82) $end
$var reg 32 "6 inst_ram(83) $end
$var reg 32 "7 inst_ram(84) $end
$var reg 32 "8 inst_ram(85) $end
$var reg 32 "9 inst_ram(86) $end
$var reg 32 ": inst_ram(87) $end
$var reg 32 "; inst_ram(88) $end
$var reg 32 "< inst_ram(89) $end
$var reg 32 "= inst_ram(90) $end
$var reg 32 "> inst_ram(91) $end
$var reg 32 "? inst_ram(92) $end
$var reg 32 "@ inst_ram(93) $end
$var reg 32 "A inst_ram(94) $end
$var reg 32 "B inst_ram(95) $end
$var reg 32 "C inst_ram(96) $end
$var reg 32 "D inst_ram(97) $end
$var reg 32 "E inst_ram(98) $end
$var reg 32 "F inst_ram(99) $end
$var reg 32 "G inst_ram(100) $end
$var reg 32 "H inst_ram(101) $end
$var reg 32 "I inst_ram(102) $end
$var reg 32 "J inst_ram(103) $end
$var reg 32 "K inst_ram(104) $end
$var reg 32 "L inst_ram(105) $end
$var reg 32 "M inst_ram(106) $end
$var reg 32 "N inst_ram(107) $end
$var reg 32 "O inst_ram(108) $end
$var reg 32 "P inst_ram(109) $end
$var reg 32 "Q inst_ram(110) $end
$var reg 32 "R inst_ram(111) $end
$var reg 32 "S inst_ram(112) $end
$var reg 32 "T inst_ram(113) $end
$var reg 32 "U inst_ram(114) $end
$var reg 32 "V inst_ram(115) $end
$var reg 32 "W inst_ram(116) $end
$var reg 32 "X inst_ram(117) $end
$var reg 32 "Y inst_ram(118) $end
$var reg 32 "Z inst_ram(119) $end
$var reg 32 "[ inst_ram(120) $end
$var reg 32 "\ inst_ram(121) $end
$var reg 32 "] inst_ram(122) $end
$var reg 32 "^ inst_ram(123) $end
$var reg 32 "_ inst_ram(124) $end
$var reg 32 "` inst_ram(125) $end
$var reg 32 "a inst_ram(126) $end
$var reg 32 "b inst_ram(127) $end
$upscope $end
$upscope $end
$scope module ifid_pipl $end
$var reg 64 5 ifid_reg $end
$var reg 32 ' instruction $end
$var reg 32 # pc $end
$var reg 1 " reset $end
$upscope $end
$scope module decode $end
$var reg 64 5 ifid_reg $end
$var reg 7 8 opcode $end
$var reg 5 ( ra $end
$var reg 5 ) rb $end
$var reg 1 " reset $end
$var reg 5 * wa $end
$upscope $end
$scope module reg_file $end
$var reg 1 ! clk $end
$var reg 5 ( ra $end
$var reg 5 ) rb $end
$var reg 32 , rda $end
$var reg 32 - rdb $end
$var reg 1 4 reg_wr $end
$var reg 1 " reset $end
$var reg 5 * wa $end
$var reg 32 + wda $end
$scope module registers $end
$var reg 32 "c registers(0) $end
$var reg 32 "d registers(1) $end
$var reg 32 "e registers(2) $end
$var reg 32 "f registers(3) $end
$var reg 32 "g registers(4) $end
$var reg 32 "h registers(5) $end
$var reg 32 "i registers(6) $end
$var reg 32 "j registers(7) $end
$var reg 32 "k registers(8) $end
$var reg 32 "l registers(9) $end
$var reg 32 "m registers(10) $end
$var reg 32 "n registers(11) $end
$var reg 32 "o registers(12) $end
$var reg 32 "p registers(13) $end
$var reg 32 "q registers(14) $end
$var reg 32 "r registers(15) $end
$var reg 32 "s registers(16) $end
$var reg 32 "t registers(17) $end
$var reg 32 "u registers(18) $end
$var reg 32 "v registers(19) $end
$var reg 32 "w registers(20) $end
$var reg 32 "x registers(21) $end
$var reg 32 "y registers(22) $end
$var reg 32 "z registers(23) $end
$var reg 32 "{ registers(24) $end
$var reg 32 "| registers(25) $end
$var reg 32 "} registers(26) $end
$var reg 32 "~ registers(27) $end
$var reg 32 #! registers(28) $end
$var reg 32 #" registers(29) $end
$var reg 32 ## registers(30) $end
$var reg 32 #$ registers(31) $end
$upscope $end
$upscope $end
$scope module control $end
$var reg 4 9 alu_op $end
$var reg 1 3 alu_src $end
$var reg 1 / brnch $end
$var reg 1 0 mem_rd $end
$var reg 1 1 mem_to_rgs $end
$var reg 1 2 mem_wr $end
$var reg 7 8 opcode $end
$var reg 1 4 reg_wr $end
$var reg 1 " reset $end
$upscope $end
$scope module imm_gen $end
$var reg 64 5 ifid_reg $end
$var reg 32 : im_gen $end
$var reg 20 < padx $end
$var reg 20 ; padz $end
$var reg 1 " reset $end
$upscope $end
$scope module idex_pipl $end
$var reg 4 9 alu_op $end
$var reg 1 3 alu_src $end
$var reg 1 / brnch $end
$var reg 153 @ idex_reg $end
$var reg 32 : im_gen $end
$var reg 32 ' instruction $end
$var reg 1 0 mem_rd $end
$var reg 1 1 mem_to_rgs $end
$var reg 1 2 mem_wr $end
$var reg 5 ( ra $end
$var reg 5 ) rb $end
$var reg 32 , rda $end
$var reg 32 - rdb $end
$var reg 1 4 reg_wr $end
$var reg 1 " reset $end
$var reg 5 * wa $end
$upscope $end
$scope module alu_control $end
$var reg 4 6 alu_decode $end
$var reg 153 @ idex_reg $end
$var reg 1 " reset $end
$upscope $end
$scope module alu $end
$var reg 4 6 alu_decode $end
$var reg 153 @ idex_reg $end
$var reg 32 . rdx $end
$var reg 1 " reset $end
$var reg 32 = result $end
$upscope $end
$upscope $end
$upscope $end

$enddefinitions $end
$dumpvars
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$end
#10
b1 !
#20
b0 !
1"
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