3378 lines
133 KiB
Plaintext
3378 lines
133 KiB
Plaintext
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$version Generated by VerilatedVcd $end
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$date Sat May 1 15:29:14 2021
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$end
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$timescale 1ns $end
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$scope module TOP $end
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$var wire 1 +d clk $end
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$var wire 1 Cd failed $end
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$var wire 1 ;d passed $end
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$var wire 1 3d reset_async $end
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$scope module makerchip $end
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$var wire 1 +d clk $end
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$var wire 32 k@ cyc_cnt [31:0] $end
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$var wire 1 Cd failed $end
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$var wire 1 ;d passed $end
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$var wire 1 c@ reset $end
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$var wire 1 3d reset_async $end
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$scope module top $end
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$var wire 32 {< CPU_Dmem_value_a4(0) [31:0] $end
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$var wire 32 |< CPU_Dmem_value_a4(1) [31:0] $end
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$var wire 32 '= CPU_Dmem_value_a4(10) [31:0] $end
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$var wire 32 (= CPU_Dmem_value_a4(11) [31:0] $end
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$var wire 32 )= CPU_Dmem_value_a4(12) [31:0] $end
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$var wire 32 *= CPU_Dmem_value_a4(13) [31:0] $end
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$var wire 32 += CPU_Dmem_value_a4(14) [31:0] $end
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$var wire 32 ,= CPU_Dmem_value_a4(15) [31:0] $end
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$var wire 32 }< CPU_Dmem_value_a4(2) [31:0] $end
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$var wire 32 ~< CPU_Dmem_value_a4(3) [31:0] $end
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$var wire 32 != CPU_Dmem_value_a4(4) [31:0] $end
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$var wire 32 "= CPU_Dmem_value_a4(5) [31:0] $end
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$var wire 32 #= CPU_Dmem_value_a4(6) [31:0] $end
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$var wire 32 $= CPU_Dmem_value_a4(7) [31:0] $end
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$var wire 32 %= CPU_Dmem_value_a4(8) [31:0] $end
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$var wire 32 &= CPU_Dmem_value_a4(9) [31:0] $end
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$var wire 32 Ob CPU_Dmem_value_a5(0) [31:0] $end
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$var wire 32 Pb CPU_Dmem_value_a5(1) [31:0] $end
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$var wire 32 Yb CPU_Dmem_value_a5(10) [31:0] $end
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$var wire 32 Zb CPU_Dmem_value_a5(11) [31:0] $end
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$var wire 32 [b CPU_Dmem_value_a5(12) [31:0] $end
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$var wire 32 \b CPU_Dmem_value_a5(13) [31:0] $end
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$var wire 32 ]b CPU_Dmem_value_a5(14) [31:0] $end
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$var wire 32 ^b CPU_Dmem_value_a5(15) [31:0] $end
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$var wire 32 Qb CPU_Dmem_value_a5(2) [31:0] $end
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$var wire 32 Rb CPU_Dmem_value_a5(3) [31:0] $end
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$var wire 32 Sb CPU_Dmem_value_a5(4) [31:0] $end
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$var wire 32 Tb CPU_Dmem_value_a5(5) [31:0] $end
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$var wire 32 Ub CPU_Dmem_value_a5(6) [31:0] $end
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$var wire 32 Vb CPU_Dmem_value_a5(7) [31:0] $end
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$var wire 32 Wb CPU_Dmem_value_a5(8) [31:0] $end
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$var wire 32 Xb CPU_Dmem_value_a5(9) [31:0] $end
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$var wire 32 # CPU_Imem_instr_a1(0) [31:0] $end
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$var wire 32 $ CPU_Imem_instr_a1(1) [31:0] $end
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$var wire 32 % CPU_Imem_instr_a1(2) [31:0] $end
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$var wire 32 & CPU_Imem_instr_a1(3) [31:0] $end
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$var wire 32 ' CPU_Imem_instr_a1(4) [31:0] $end
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$var wire 32 ( CPU_Imem_instr_a1(5) [31:0] $end
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$var wire 32 ) CPU_Imem_instr_a1(6) [31:0] $end
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$var wire 32 * CPU_Imem_instr_a1(7) [31:0] $end
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$var wire 64 /& CPU_Xreg_value_a3(0) [63:0] $end
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$var wire 64 1& CPU_Xreg_value_a3(1) [63:0] $end
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$var wire 64 C& CPU_Xreg_value_a3(10) [63:0] $end
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$var wire 64 E& CPU_Xreg_value_a3(11) [63:0] $end
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$var wire 64 G& CPU_Xreg_value_a3(12) [63:0] $end
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$var wire 64 I& CPU_Xreg_value_a3(13) [63:0] $end
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$var wire 64 K& CPU_Xreg_value_a3(14) [63:0] $end
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$var wire 64 M& CPU_Xreg_value_a3(15) [63:0] $end
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$var wire 64 O& CPU_Xreg_value_a3(16) [63:0] $end
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$var wire 64 Q& CPU_Xreg_value_a3(17) [63:0] $end
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$var wire 64 S& CPU_Xreg_value_a3(18) [63:0] $end
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$var wire 64 U& CPU_Xreg_value_a3(19) [63:0] $end
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$var wire 64 3& CPU_Xreg_value_a3(2) [63:0] $end
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$var wire 64 W& CPU_Xreg_value_a3(20) [63:0] $end
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$var wire 64 Y& CPU_Xreg_value_a3(21) [63:0] $end
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$var wire 64 [& CPU_Xreg_value_a3(22) [63:0] $end
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$var wire 64 ]& CPU_Xreg_value_a3(23) [63:0] $end
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$var wire 64 _& CPU_Xreg_value_a3(24) [63:0] $end
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$var wire 64 a& CPU_Xreg_value_a3(25) [63:0] $end
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$var wire 64 c& CPU_Xreg_value_a3(26) [63:0] $end
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$var wire 64 e& CPU_Xreg_value_a3(27) [63:0] $end
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$var wire 64 g& CPU_Xreg_value_a3(28) [63:0] $end
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$var wire 64 i& CPU_Xreg_value_a3(29) [63:0] $end
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$var wire 64 5& CPU_Xreg_value_a3(3) [63:0] $end
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$var wire 64 k& CPU_Xreg_value_a3(30) [63:0] $end
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$var wire 64 m& CPU_Xreg_value_a3(31) [63:0] $end
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$var wire 64 o& CPU_Xreg_value_a3(32) [63:0] $end
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$var wire 64 q& CPU_Xreg_value_a3(33) [63:0] $end
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$var wire 64 s& CPU_Xreg_value_a3(34) [63:0] $end
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$var wire 64 u& CPU_Xreg_value_a3(35) [63:0] $end
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$var wire 64 w& CPU_Xreg_value_a3(36) [63:0] $end
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$var wire 64 y& CPU_Xreg_value_a3(37) [63:0] $end
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$var wire 64 {& CPU_Xreg_value_a3(38) [63:0] $end
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$var wire 64 }& CPU_Xreg_value_a3(39) [63:0] $end
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$var wire 64 7& CPU_Xreg_value_a3(4) [63:0] $end
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$var wire 64 !' CPU_Xreg_value_a3(40) [63:0] $end
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$var wire 64 #' CPU_Xreg_value_a3(41) [63:0] $end
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$var wire 64 %' CPU_Xreg_value_a3(42) [63:0] $end
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$var wire 64 '' CPU_Xreg_value_a3(43) [63:0] $end
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$var wire 64 )' CPU_Xreg_value_a3(44) [63:0] $end
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$var wire 64 +' CPU_Xreg_value_a3(45) [63:0] $end
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$var wire 64 -' CPU_Xreg_value_a3(46) [63:0] $end
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$var wire 64 /' CPU_Xreg_value_a3(47) [63:0] $end
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$var wire 64 1' CPU_Xreg_value_a3(48) [63:0] $end
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$var wire 64 3' CPU_Xreg_value_a3(49) [63:0] $end
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$var wire 64 9& CPU_Xreg_value_a3(5) [63:0] $end
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$var wire 64 5' CPU_Xreg_value_a3(50) [63:0] $end
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$var wire 64 7' CPU_Xreg_value_a3(51) [63:0] $end
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$var wire 64 9' CPU_Xreg_value_a3(52) [63:0] $end
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$var wire 64 ;' CPU_Xreg_value_a3(53) [63:0] $end
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$var wire 64 =' CPU_Xreg_value_a3(54) [63:0] $end
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$var wire 64 ?' CPU_Xreg_value_a3(55) [63:0] $end
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$var wire 64 A' CPU_Xreg_value_a3(56) [63:0] $end
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$var wire 64 C' CPU_Xreg_value_a3(57) [63:0] $end
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$var wire 64 E' CPU_Xreg_value_a3(58) [63:0] $end
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$var wire 64 G' CPU_Xreg_value_a3(59) [63:0] $end
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$var wire 64 ;& CPU_Xreg_value_a3(6) [63:0] $end
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$var wire 64 I' CPU_Xreg_value_a3(60) [63:0] $end
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$var wire 64 K' CPU_Xreg_value_a3(61) [63:0] $end
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$var wire 64 M' CPU_Xreg_value_a3(62) [63:0] $end
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$var wire 64 O' CPU_Xreg_value_a3(63) [63:0] $end
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$var wire 64 =& CPU_Xreg_value_a3(7) [63:0] $end
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$var wire 64 ?& CPU_Xreg_value_a3(8) [63:0] $end
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$var wire 64 A& CPU_Xreg_value_a3(9) [63:0] $end
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$var wire 64 9K CPU_Xreg_value_a4(0) [63:0] $end
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$var wire 64 ;K CPU_Xreg_value_a4(1) [63:0] $end
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$var wire 64 MK CPU_Xreg_value_a4(10) [63:0] $end
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$var wire 64 OK CPU_Xreg_value_a4(11) [63:0] $end
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$var wire 64 QK CPU_Xreg_value_a4(12) [63:0] $end
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$var wire 64 SK CPU_Xreg_value_a4(13) [63:0] $end
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$var wire 64 UK CPU_Xreg_value_a4(14) [63:0] $end
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$var wire 64 WK CPU_Xreg_value_a4(15) [63:0] $end
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$var wire 64 YK CPU_Xreg_value_a4(16) [63:0] $end
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$var wire 64 [K CPU_Xreg_value_a4(17) [63:0] $end
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$var wire 64 ]K CPU_Xreg_value_a4(18) [63:0] $end
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$var wire 64 _K CPU_Xreg_value_a4(19) [63:0] $end
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$var wire 64 =K CPU_Xreg_value_a4(2) [63:0] $end
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$var wire 64 aK CPU_Xreg_value_a4(20) [63:0] $end
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$var wire 64 cK CPU_Xreg_value_a4(21) [63:0] $end
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$var wire 64 eK CPU_Xreg_value_a4(22) [63:0] $end
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$var wire 64 gK CPU_Xreg_value_a4(23) [63:0] $end
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$var wire 64 iK CPU_Xreg_value_a4(24) [63:0] $end
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$var wire 64 kK CPU_Xreg_value_a4(25) [63:0] $end
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$var wire 64 mK CPU_Xreg_value_a4(26) [63:0] $end
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$var wire 64 oK CPU_Xreg_value_a4(27) [63:0] $end
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$var wire 64 qK CPU_Xreg_value_a4(28) [63:0] $end
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$var wire 64 sK CPU_Xreg_value_a4(29) [63:0] $end
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$var wire 64 ?K CPU_Xreg_value_a4(3) [63:0] $end
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$var wire 64 uK CPU_Xreg_value_a4(30) [63:0] $end
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$var wire 64 wK CPU_Xreg_value_a4(31) [63:0] $end
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$var wire 64 yK CPU_Xreg_value_a4(32) [63:0] $end
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$var wire 64 {K CPU_Xreg_value_a4(33) [63:0] $end
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$var wire 64 }K CPU_Xreg_value_a4(34) [63:0] $end
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$var wire 64 !L CPU_Xreg_value_a4(35) [63:0] $end
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$var wire 64 #L CPU_Xreg_value_a4(36) [63:0] $end
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$var wire 64 %L CPU_Xreg_value_a4(37) [63:0] $end
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$var wire 64 'L CPU_Xreg_value_a4(38) [63:0] $end
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$var wire 64 )L CPU_Xreg_value_a4(39) [63:0] $end
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$var wire 64 AK CPU_Xreg_value_a4(4) [63:0] $end
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$var wire 64 +L CPU_Xreg_value_a4(40) [63:0] $end
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$var wire 64 -L CPU_Xreg_value_a4(41) [63:0] $end
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$var wire 64 /L CPU_Xreg_value_a4(42) [63:0] $end
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$var wire 64 1L CPU_Xreg_value_a4(43) [63:0] $end
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$var wire 64 3L CPU_Xreg_value_a4(44) [63:0] $end
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$var wire 64 5L CPU_Xreg_value_a4(45) [63:0] $end
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$var wire 64 7L CPU_Xreg_value_a4(46) [63:0] $end
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$var wire 64 9L CPU_Xreg_value_a4(47) [63:0] $end
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$var wire 64 ;L CPU_Xreg_value_a4(48) [63:0] $end
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$var wire 64 =L CPU_Xreg_value_a4(49) [63:0] $end
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$var wire 64 CK CPU_Xreg_value_a4(5) [63:0] $end
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$var wire 64 ?L CPU_Xreg_value_a4(50) [63:0] $end
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$var wire 64 AL CPU_Xreg_value_a4(51) [63:0] $end
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$var wire 64 CL CPU_Xreg_value_a4(52) [63:0] $end
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$var wire 64 EL CPU_Xreg_value_a4(53) [63:0] $end
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$var wire 64 GL CPU_Xreg_value_a4(54) [63:0] $end
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$var wire 64 IL CPU_Xreg_value_a4(55) [63:0] $end
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$var wire 64 KL CPU_Xreg_value_a4(56) [63:0] $end
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$var wire 64 ML CPU_Xreg_value_a4(57) [63:0] $end
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$var wire 64 OL CPU_Xreg_value_a4(58) [63:0] $end
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$var wire 64 QL CPU_Xreg_value_a4(59) [63:0] $end
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$var wire 64 EK CPU_Xreg_value_a4(6) [63:0] $end
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$var wire 64 SL CPU_Xreg_value_a4(60) [63:0] $end
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$var wire 64 UL CPU_Xreg_value_a4(61) [63:0] $end
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$var wire 64 WL CPU_Xreg_value_a4(62) [63:0] $end
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$var wire 64 YL CPU_Xreg_value_a4(63) [63:0] $end
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$var wire 64 GK CPU_Xreg_value_a4(7) [63:0] $end
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$var wire 64 IK CPU_Xreg_value_a4(8) [63:0] $end
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$var wire 64 KK CPU_Xreg_value_a4(9) [63:0] $end
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$var wire 64 /V CPU_Xreg_value_a5(0) [63:0] $end
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$var wire 64 1V CPU_Xreg_value_a5(1) [63:0] $end
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$var wire 64 CV CPU_Xreg_value_a5(10) [63:0] $end
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$var wire 64 EV CPU_Xreg_value_a5(11) [63:0] $end
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$var wire 64 GV CPU_Xreg_value_a5(12) [63:0] $end
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$var wire 64 IV CPU_Xreg_value_a5(13) [63:0] $end
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$var wire 64 KV CPU_Xreg_value_a5(14) [63:0] $end
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$var wire 64 MV CPU_Xreg_value_a5(15) [63:0] $end
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$var wire 64 OV CPU_Xreg_value_a5(16) [63:0] $end
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$var wire 64 QV CPU_Xreg_value_a5(17) [63:0] $end
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$var wire 64 SV CPU_Xreg_value_a5(18) [63:0] $end
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$var wire 64 UV CPU_Xreg_value_a5(19) [63:0] $end
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$var wire 64 3V CPU_Xreg_value_a5(2) [63:0] $end
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$var wire 64 WV CPU_Xreg_value_a5(20) [63:0] $end
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$var wire 64 YV CPU_Xreg_value_a5(21) [63:0] $end
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$var wire 64 [V CPU_Xreg_value_a5(22) [63:0] $end
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$var wire 64 ]V CPU_Xreg_value_a5(23) [63:0] $end
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$var wire 64 _V CPU_Xreg_value_a5(24) [63:0] $end
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$var wire 64 aV CPU_Xreg_value_a5(25) [63:0] $end
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$var wire 64 cV CPU_Xreg_value_a5(26) [63:0] $end
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$var wire 64 eV CPU_Xreg_value_a5(27) [63:0] $end
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$var wire 64 gV CPU_Xreg_value_a5(28) [63:0] $end
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$var wire 64 iV CPU_Xreg_value_a5(29) [63:0] $end
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$var wire 64 5V CPU_Xreg_value_a5(3) [63:0] $end
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$var wire 64 kV CPU_Xreg_value_a5(30) [63:0] $end
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$var wire 64 mV CPU_Xreg_value_a5(31) [63:0] $end
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$var wire 64 oV CPU_Xreg_value_a5(32) [63:0] $end
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$var wire 64 qV CPU_Xreg_value_a5(33) [63:0] $end
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$var wire 64 sV CPU_Xreg_value_a5(34) [63:0] $end
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$var wire 64 uV CPU_Xreg_value_a5(35) [63:0] $end
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$var wire 64 wV CPU_Xreg_value_a5(36) [63:0] $end
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$var wire 64 yV CPU_Xreg_value_a5(37) [63:0] $end
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|
|
$var wire 64 {V CPU_Xreg_value_a5(38) [63:0] $end
|
||
|
|
$var wire 64 }V CPU_Xreg_value_a5(39) [63:0] $end
|
||
|
|
$var wire 64 7V CPU_Xreg_value_a5(4) [63:0] $end
|
||
|
|
$var wire 64 !W CPU_Xreg_value_a5(40) [63:0] $end
|
||
|
|
$var wire 64 #W CPU_Xreg_value_a5(41) [63:0] $end
|
||
|
|
$var wire 64 %W CPU_Xreg_value_a5(42) [63:0] $end
|
||
|
|
$var wire 64 'W CPU_Xreg_value_a5(43) [63:0] $end
|
||
|
|
$var wire 64 )W CPU_Xreg_value_a5(44) [63:0] $end
|
||
|
|
$var wire 64 +W CPU_Xreg_value_a5(45) [63:0] $end
|
||
|
|
$var wire 64 -W CPU_Xreg_value_a5(46) [63:0] $end
|
||
|
|
$var wire 64 /W CPU_Xreg_value_a5(47) [63:0] $end
|
||
|
|
$var wire 64 1W CPU_Xreg_value_a5(48) [63:0] $end
|
||
|
|
$var wire 64 3W CPU_Xreg_value_a5(49) [63:0] $end
|
||
|
|
$var wire 64 9V CPU_Xreg_value_a5(5) [63:0] $end
|
||
|
|
$var wire 64 5W CPU_Xreg_value_a5(50) [63:0] $end
|
||
|
|
$var wire 64 7W CPU_Xreg_value_a5(51) [63:0] $end
|
||
|
|
$var wire 64 9W CPU_Xreg_value_a5(52) [63:0] $end
|
||
|
|
$var wire 64 ;W CPU_Xreg_value_a5(53) [63:0] $end
|
||
|
|
$var wire 64 =W CPU_Xreg_value_a5(54) [63:0] $end
|
||
|
|
$var wire 64 ?W CPU_Xreg_value_a5(55) [63:0] $end
|
||
|
|
$var wire 64 AW CPU_Xreg_value_a5(56) [63:0] $end
|
||
|
|
$var wire 64 CW CPU_Xreg_value_a5(57) [63:0] $end
|
||
|
|
$var wire 64 EW CPU_Xreg_value_a5(58) [63:0] $end
|
||
|
|
$var wire 64 GW CPU_Xreg_value_a5(59) [63:0] $end
|
||
|
|
$var wire 64 ;V CPU_Xreg_value_a5(6) [63:0] $end
|
||
|
|
$var wire 64 IW CPU_Xreg_value_a5(60) [63:0] $end
|
||
|
|
$var wire 64 KW CPU_Xreg_value_a5(61) [63:0] $end
|
||
|
|
$var wire 64 MW CPU_Xreg_value_a5(62) [63:0] $end
|
||
|
|
$var wire 64 OW CPU_Xreg_value_a5(63) [63:0] $end
|
||
|
|
$var wire 64 =V CPU_Xreg_value_a5(7) [63:0] $end
|
||
|
|
$var wire 64 ?V CPU_Xreg_value_a5(8) [63:0] $end
|
||
|
|
$var wire 64 AV CPU_Xreg_value_a5(9) [63:0] $end
|
||
|
|
$var wire 32 OB CPU_br_tgt_pc_a2 [31:0] $end
|
||
|
|
$var wire 32 WB CPU_br_tgt_pc_a3 [31:0] $end
|
||
|
|
$var wire 1 7b CPU_dmem_addr_a4 $end
|
||
|
|
$var wire 1 _B CPU_dmem_addr_a5 $end
|
||
|
|
$var wire 32 ?b CPU_dmem_rd_data_a4 [31:0] $end
|
||
|
|
$var wire 32 ua CPU_dmem_rd_data_a5 [31:0] $end
|
||
|
|
$var wire 1 gB CPU_dmem_rd_en_a4 $end
|
||
|
|
$var wire 1 oB CPU_dmem_rd_en_a5 $end
|
||
|
|
$var wire 64 wB CPU_dmem_wr_data_a4 [63:0] $end
|
||
|
|
$var wire 64 )C CPU_dmem_wr_data_a5 [63:0] $end
|
||
|
|
$var wire 1 '" CPU_dmem_wr_en_a4 $end
|
||
|
|
$var wire 1 9C CPU_dmem_wr_en_a5 $end
|
||
|
|
$var wire 3 AC CPU_imem_rd_addr_a1 [2:0] $end
|
||
|
|
$var wire 3 IC CPU_imem_rd_addr_a2 [2:0] $end
|
||
|
|
$var wire 3 QC CPU_imem_rd_addr_a3 [2:0] $end
|
||
|
|
$var wire 3 YC CPU_imem_rd_addr_a4 [2:0] $end
|
||
|
|
$var wire 3 aC CPU_imem_rd_addr_a5 [2:0] $end
|
||
|
|
$var wire 32 y? CPU_imem_rd_data_a1 [31:0] $end
|
||
|
|
$var wire 1 iC CPU_imem_rd_en_a1 $end
|
||
|
|
$var wire 1 qC CPU_imem_rd_en_a2 $end
|
||
|
|
$var wire 1 yC CPU_imem_rd_en_a3 $end
|
||
|
|
$var wire 1 #D CPU_imem_rd_en_a4 $end
|
||
|
|
$var wire 1 +D CPU_imem_rd_en_a5 $end
|
||
|
|
$var wire 64 #@ CPU_imm_a1 [63:0] $end
|
||
|
|
$var wire 64 3D CPU_imm_a2 [63:0] $end
|
||
|
|
$var wire 64 CD CPU_imm_a3 [63:0] $end
|
||
|
|
$var wire 64 SD CPU_imm_a4 [63:0] $end
|
||
|
|
$var wire 64 cD CPU_imm_a5 [63:0] $end
|
||
|
|
$var wire 32 sD CPU_inc_pc_a1 [31:0] $end
|
||
|
|
$var wire 32 y? CPU_instr_a1 [31:0] $end
|
||
|
|
$var wire 1 {D CPU_is_add_a2 $end
|
||
|
|
$var wire 1 %E CPU_is_add_a3 $end
|
||
|
|
$var wire 1 -E CPU_is_addi_a2 $end
|
||
|
|
$var wire 1 5E CPU_is_addi_a3 $end
|
||
|
|
$var wire 1 =E CPU_is_and_a2 $end
|
||
|
|
$var wire 1 EE CPU_is_and_a3 $end
|
||
|
|
$var wire 1 ME CPU_is_andi_a2 $end
|
||
|
|
$var wire 1 UE CPU_is_andi_a3 $end
|
||
|
|
$var wire 1 ]E CPU_is_b_a2 $end
|
||
|
|
$var wire 1 eE CPU_is_b_a3 $end
|
||
|
|
$var wire 1 mE CPU_is_b_a4 $end
|
||
|
|
$var wire 1 uE CPU_is_b_a5 $end
|
||
|
|
$var wire 1 }E CPU_is_ld_a2 $end
|
||
|
|
$var wire 1 'F CPU_is_ld_a3 $end
|
||
|
|
$var wire 1 gB CPU_is_ld_a4 $end
|
||
|
|
$var wire 1 /F CPU_is_ld_a5 $end
|
||
|
|
$var wire 1 7F CPU_is_nand_a2 $end
|
||
|
|
$var wire 1 ?F CPU_is_nand_a3 $end
|
||
|
|
$var wire 1 GF CPU_is_or_a2 $end
|
||
|
|
$var wire 1 OF CPU_is_or_a3 $end
|
||
|
|
$var wire 1 WF CPU_is_ori_a2 $end
|
||
|
|
$var wire 1 _F CPU_is_ori_a3 $end
|
||
|
|
$var wire 1 gF CPU_is_std_a2 $end
|
||
|
|
$var wire 1 oF CPU_is_std_a3 $end
|
||
|
|
$var wire 1 wF CPU_is_std_a4 $end
|
||
|
|
$var wire 1 !G CPU_is_std_a5 $end
|
||
|
|
$var wire 1 )G CPU_is_sub_a2 $end
|
||
|
|
$var wire 1 1G CPU_is_sub_a3 $end
|
||
|
|
$var wire 64 }a CPU_ld_data_a5 [63:0] $end
|
||
|
|
$var wire 32 /" CPU_pc_a0 [31:0] $end
|
||
|
|
$var wire 32 9G CPU_pc_a1 [31:0] $end
|
||
|
|
$var wire 32 AG CPU_pc_a2 [31:0] $end
|
||
|
|
$var wire 6 3@ CPU_po_bits_a1 [5:0] $end
|
||
|
|
$var wire 6 IG CPU_po_bits_a2 [5:0] $end
|
||
|
|
$var wire 5 ;@ CPU_rd_a1 [4:0] $end
|
||
|
|
$var wire 5 #d CPU_rd_a2 [4:0] $end
|
||
|
|
$var wire 5 yc CPU_rd_a3 [4:0] $end
|
||
|
|
$var wire 5 qc CPU_rd_a4 [4:0] $end
|
||
|
|
$var wire 5 /b CPU_rd_a5 [4:0] $end
|
||
|
|
$var wire 1 C@ CPU_rd_valid_a1 $end
|
||
|
|
$var wire 1 QG CPU_rd_valid_a2 $end
|
||
|
|
$var wire 1 YG CPU_rd_valid_a3 $end
|
||
|
|
$var wire 1 aG CPU_rd_valid_a4 $end
|
||
|
|
$var wire 1 c@ CPU_reset_a0 $end
|
||
|
|
$var wire 1 iG CPU_reset_a1 $end
|
||
|
|
$var wire 1 qG CPU_reset_a2 $end
|
||
|
|
$var wire 1 yG CPU_reset_a3 $end
|
||
|
|
$var wire 1 #H CPU_reset_a4 $end
|
||
|
|
$var wire 64 k< CPU_result_a3 [63:0] $end
|
||
|
|
$var wire 4 Gb CPU_result_a4 [5:2] $end
|
||
|
|
$var wire 64 +H CPU_rf_rd_data1_a2 [63:0] $end
|
||
|
|
$var wire 64 7" CPU_rf_rd_data2_a2 [63:0] $end
|
||
|
|
$var wire 1 Kd CPU_rf_rd_en1_a2 $end
|
||
|
|
$var wire 1 Kd CPU_rf_rd_en2_a2 $end
|
||
|
|
$var wire 5 ;H CPU_rf_rd_index1_a2 [4:0] $end
|
||
|
|
$var wire 5 CH CPU_rf_rd_index2_a2 [4:0] $end
|
||
|
|
$var wire 5 KH CPU_rf_rd_index2_a3 [4:0] $end
|
||
|
|
$var wire 5 SH CPU_rf_rd_index2_a4 [4:0] $end
|
||
|
|
$var wire 5 [H CPU_rf_rd_index2_a5 [4:0] $end
|
||
|
|
$var wire 64 a? CPU_rf_wr_data_a3 [63:0] $end
|
||
|
|
$var wire 1 G" CPU_rf_wr_en_a3 $end
|
||
|
|
$var wire 5 q? CPU_rf_wr_index_a3 [4:0] $end
|
||
|
|
$var wire 5 K@ CPU_rs1_a1 [4:0] $end
|
||
|
|
$var wire 5 ;H CPU_rs1_a2 [4:0] $end
|
||
|
|
$var wire 5 cH CPU_rs1_a3 [4:0] $end
|
||
|
|
$var wire 5 kH CPU_rs1_a4 [4:0] $end
|
||
|
|
$var wire 5 sH CPU_rs1_a5 [4:0] $end
|
||
|
|
$var wire 5 S@ CPU_rs2_a1 [4:0] $end
|
||
|
|
$var wire 5 CH CPU_rs2_a2 [4:0] $end
|
||
|
|
$var wire 5 {H CPU_rs2_a3 [4:0] $end
|
||
|
|
$var wire 5 %I CPU_rs2_a4 [4:0] $end
|
||
|
|
$var wire 5 -I CPU_rs2_a5 [4:0] $end
|
||
|
|
$var wire 64 w" CPU_src1_value_a2 [63:0] $end
|
||
|
|
$var wire 64 5I CPU_src1_value_a3 [63:0] $end
|
||
|
|
$var wire 64 )# CPU_src2_value_a2 [63:0] $end
|
||
|
|
$var wire 64 EI CPU_src2_value_a3 [63:0] $end
|
||
|
|
$var wire 64 wB CPU_src2_value_a4 [63:0] $end
|
||
|
|
$var wire 64 9# CPU_src3_value_a2 [63:0] $end
|
||
|
|
$var wire 64 UI CPU_src3_value_a3 [63:0] $end
|
||
|
|
$var wire 64 eI CPU_src3_value_a4 [63:0] $end
|
||
|
|
$var wire 64 uI CPU_src3_value_a5 [63:0] $end
|
||
|
|
$var wire 1 'J CPU_start_a0 $end
|
||
|
|
$var wire 1 /J CPU_start_a1 $end
|
||
|
|
$var wire 1 7J CPU_start_a2 $end
|
||
|
|
$var wire 1 ?J CPU_start_a3 $end
|
||
|
|
$var wire 1 GJ CPU_start_a4 $end
|
||
|
|
$var wire 1 OJ CPU_start_a5 $end
|
||
|
|
$var wire 1 WJ CPU_taken_br_a3 $end
|
||
|
|
$var wire 1 _J CPU_temp_a2 $end
|
||
|
|
$var wire 1 O" CPU_valid_a3 $end
|
||
|
|
$var wire 1 gJ CPU_valid_a4 $end
|
||
|
|
$var wire 1 W" CPU_valid_load_a3 $end
|
||
|
|
$var wire 1 oJ CPU_valid_load_a4 $end
|
||
|
|
$var wire 1 wJ CPU_valid_load_a5 $end
|
||
|
|
$var wire 1 _" CPU_valid_taken_br_a3 $end
|
||
|
|
$var wire 1 !K CPU_valid_taken_br_a4 $end
|
||
|
|
$var wire 1 )K CPU_valid_taken_br_a5 $end
|
||
|
|
$var wire 10 [@ CPU_xo_bits_a1 [9:0] $end
|
||
|
|
$var wire 10 1K CPU_xo_bits_a2 [9:0] $end
|
||
|
|
$var wire 257 s@ RW_rand_raw [256:0] $end
|
||
|
|
$var wire 320 ]A RW_rand_vect [319:0] $end
|
||
|
|
$var wire 1 +d clk $end
|
||
|
|
$var wire 1 y; clkP_CPU_dmem_rd_en_a5 $end
|
||
|
|
$var wire 1 #< clkP_CPU_rd_valid_a2 $end
|
||
|
|
$var wire 1 +< clkP_CPU_rd_valid_a3 $end
|
||
|
|
$var wire 1 3< clkP_CPU_rd_valid_a4 $end
|
||
|
|
$var wire 1 ;< clkP_CPU_rd_valid_a5 $end
|
||
|
|
$var wire 32 k@ cyc_cnt [31:0] $end
|
||
|
|
$var wire 1 Cd failed $end
|
||
|
|
$var wire 32 c instrs(0) [31:0] $end
|
||
|
|
$var wire 32 d instrs(1) [31:0] $end
|
||
|
|
$var wire 32 e instrs(2) [31:0] $end
|
||
|
|
$var wire 32 f instrs(3) [31:0] $end
|
||
|
|
$var wire 32 g instrs(4) [31:0] $end
|
||
|
|
$var wire 32 h instrs(5) [31:0] $end
|
||
|
|
$var wire 32 i instrs(6) [31:0] $end
|
||
|
|
$var wire 32 j instrs(7) [31:0] $end
|
||
|
|
$var wire 1 ;d passed $end
|
||
|
|
$var wire 1 c@ reset $end
|
||
|
|
$scope module DEBUG_SIGS $end
|
||
|
|
$scope module |cpu $end
|
||
|
|
$var wire 32 ?b >?$dmem_rd_en@4$dmem_rd_data [31:0] $end
|
||
|
|
$var wire 32 y? >?$imem_rd_en@1$imem_rd_data [31:0] $end
|
||
|
|
$var wire 5 ;@ >?$rd_valid@1$rd [4:0] $end
|
||
|
|
$var wire 64 +H >?$rf_rd_en1@2$rf_rd_data1 [63:0] $end
|
||
|
|
$var wire 64 7" >?$rf_rd_en2@2$rf_rd_data2 [63:0] $end
|
||
|
|
$var wire 32 /" >@0$pc [31:0] $end
|
||
|
|
$var wire 1 c@ >@0$reset $end
|
||
|
|
$var wire 1 'J >@0$start $end
|
||
|
|
$var wire 3 AC >@1$imem_rd_addr [2:0] $end
|
||
|
|
$var wire 1 iC >@1$imem_rd_en $end
|
||
|
|
$var wire 64 #@ >@1$imm [63:0] $end
|
||
|
|
$var wire 32 sD >@1$inc_pc [31:0] $end
|
||
|
|
$var wire 32 y? >@1$instr [31:0] $end
|
||
|
|
$var wire 6 3@ >@1$po_bits [5:0] $end
|
||
|
|
$var wire 1 C@ >@1$rd_valid $end
|
||
|
|
$var wire 5 K@ >@1$rs1 [4:0] $end
|
||
|
|
$var wire 5 S@ >@1$rs2 [4:0] $end
|
||
|
|
$var wire 10 [@ >@1$xo_bits [9:0] $end
|
||
|
|
$var wire 32 OB >@2$br_tgt_pc [31:0] $end
|
||
|
|
$var wire 1 {D >@2$is_add $end
|
||
|
|
$var wire 1 -E >@2$is_addi $end
|
||
|
|
$var wire 1 =E >@2$is_and $end
|
||
|
|
$var wire 1 ME >@2$is_andi $end
|
||
|
|
$var wire 1 ]E >@2$is_b $end
|
||
|
|
$var wire 1 }E >@2$is_ld $end
|
||
|
|
$var wire 1 7F >@2$is_nand $end
|
||
|
|
$var wire 1 GF >@2$is_or $end
|
||
|
|
$var wire 1 WF >@2$is_ori $end
|
||
|
|
$var wire 1 gF >@2$is_std $end
|
||
|
|
$var wire 1 )G >@2$is_sub $end
|
||
|
|
$var wire 1 Kd >@2$rf_rd_en1 $end
|
||
|
|
$var wire 1 Kd >@2$rf_rd_en2 $end
|
||
|
|
$var wire 5 ;H >@2$rf_rd_index1 [4:0] $end
|
||
|
|
$var wire 5 CH >@2$rf_rd_index2 [4:0] $end
|
||
|
|
$var wire 64 w" >@2$src1_value [63:0] $end
|
||
|
|
$var wire 64 )# >@2$src2_value [63:0] $end
|
||
|
|
$var wire 64 9# >@2$src3_value [63:0] $end
|
||
|
|
$var wire 1 _J >@2$temp $end
|
||
|
|
$var wire 64 k< >@3$result [63:0] $end
|
||
|
|
$var wire 64 a? >@3$rf_wr_data [63:0] $end
|
||
|
|
$var wire 1 G" >@3$rf_wr_en $end
|
||
|
|
$var wire 5 q? >@3$rf_wr_index [4:0] $end
|
||
|
|
$var wire 1 WJ >@3$taken_br $end
|
||
|
|
$var wire 1 O" >@3$valid $end
|
||
|
|
$var wire 1 W" >@3$valid_load $end
|
||
|
|
$var wire 1 _" >@3$valid_taken_br $end
|
||
|
|
$var wire 1 7b >@4$dmem_addr $end
|
||
|
|
$var wire 1 gB >@4$dmem_rd_en $end
|
||
|
|
$var wire 64 wB >@4$dmem_wr_data [63:0] $end
|
||
|
|
$var wire 1 '" >@4$dmem_wr_en $end
|
||
|
|
$var wire 64 }a >@5$ld_data [63:0] $end
|
||
|
|
$scope module /dmem(0) $end
|
||
|
|
$var wire 32 ?> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 g" >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(10) $end
|
||
|
|
$var wire 32 1? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(11) $end
|
||
|
|
$var wire 32 9? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(12) $end
|
||
|
|
$var wire 32 A? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(13) $end
|
||
|
|
$var wire 32 I? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(14) $end
|
||
|
|
$var wire 32 Q? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(15) $end
|
||
|
|
$var wire 32 Y? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(1) $end
|
||
|
|
$var wire 32 G> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 o" >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(2) $end
|
||
|
|
$var wire 32 O> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(3) $end
|
||
|
|
$var wire 32 W> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(4) $end
|
||
|
|
$var wire 32 _> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(5) $end
|
||
|
|
$var wire 32 g> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(6) $end
|
||
|
|
$var wire 32 o> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(7) $end
|
||
|
|
$var wire 32 w> >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(8) $end
|
||
|
|
$var wire 32 !? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /dmem(9) $end
|
||
|
|
$var wire 32 )? >>@4$value [31:0] $end
|
||
|
|
$var wire 1 Sd >>@4$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(0) $end
|
||
|
|
$var wire 32 E! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(1) $end
|
||
|
|
$var wire 32 M! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(2) $end
|
||
|
|
$var wire 32 U! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(3) $end
|
||
|
|
$var wire 32 ]! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(4) $end
|
||
|
|
$var wire 32 e! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(5) $end
|
||
|
|
$var wire 32 m! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(6) $end
|
||
|
|
$var wire 32 u! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /imem(7) $end
|
||
|
|
$var wire 32 }! >>@1$instr [31:0] $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(0) $end
|
||
|
|
$var wire 64 %1 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 I# >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(10) $end
|
||
|
|
$var wire 64 g2 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 ;$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(11) $end
|
||
|
|
$var wire 64 w2 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 C$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(12) $end
|
||
|
|
$var wire 64 )3 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 K$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(13) $end
|
||
|
|
$var wire 64 93 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 S$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(14) $end
|
||
|
|
$var wire 64 I3 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 [$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(15) $end
|
||
|
|
$var wire 64 Y3 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 c$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(16) $end
|
||
|
|
$var wire 64 i3 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 k$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(17) $end
|
||
|
|
$var wire 64 y3 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 s$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(18) $end
|
||
|
|
$var wire 64 +4 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 {$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(19) $end
|
||
|
|
$var wire 64 ;4 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 %% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(1) $end
|
||
|
|
$var wire 64 51 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Q# >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(20) $end
|
||
|
|
$var wire 64 K4 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 -% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(21) $end
|
||
|
|
$var wire 64 [4 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 5% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(22) $end
|
||
|
|
$var wire 64 k4 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 =% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(23) $end
|
||
|
|
$var wire 64 {4 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 E% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(24) $end
|
||
|
|
$var wire 64 -5 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 M% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(25) $end
|
||
|
|
$var wire 64 =5 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 U% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(26) $end
|
||
|
|
$var wire 64 M5 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 ]% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(27) $end
|
||
|
|
$var wire 64 ]5 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 e% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(28) $end
|
||
|
|
$var wire 64 m5 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 m% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(29) $end
|
||
|
|
$var wire 64 }5 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 u% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(2) $end
|
||
|
|
$var wire 64 E1 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Y# >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(30) $end
|
||
|
|
$var wire 64 /6 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 }% >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(31) $end
|
||
|
|
$var wire 64 ?6 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 '& >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(32) $end
|
||
|
|
$var wire 64 O6 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(33) $end
|
||
|
|
$var wire 64 _6 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(34) $end
|
||
|
|
$var wire 64 o6 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(35) $end
|
||
|
|
$var wire 64 !7 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(36) $end
|
||
|
|
$var wire 64 17 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(37) $end
|
||
|
|
$var wire 64 A7 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(38) $end
|
||
|
|
$var wire 64 Q7 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(39) $end
|
||
|
|
$var wire 64 a7 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(3) $end
|
||
|
|
$var wire 64 U1 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 a# >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(40) $end
|
||
|
|
$var wire 64 q7 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(41) $end
|
||
|
|
$var wire 64 #8 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(42) $end
|
||
|
|
$var wire 64 38 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(43) $end
|
||
|
|
$var wire 64 C8 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(44) $end
|
||
|
|
$var wire 64 S8 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(45) $end
|
||
|
|
$var wire 64 c8 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(46) $end
|
||
|
|
$var wire 64 s8 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(47) $end
|
||
|
|
$var wire 64 %9 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(48) $end
|
||
|
|
$var wire 64 59 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(49) $end
|
||
|
|
$var wire 64 E9 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(4) $end
|
||
|
|
$var wire 64 e1 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 i# >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(50) $end
|
||
|
|
$var wire 64 U9 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(51) $end
|
||
|
|
$var wire 64 e9 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(52) $end
|
||
|
|
$var wire 64 u9 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(53) $end
|
||
|
|
$var wire 64 ': >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(54) $end
|
||
|
|
$var wire 64 7: >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(55) $end
|
||
|
|
$var wire 64 G: >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(56) $end
|
||
|
|
$var wire 64 W: >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(57) $end
|
||
|
|
$var wire 64 g: >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(58) $end
|
||
|
|
$var wire 64 w: >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(59) $end
|
||
|
|
$var wire 64 ); >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(5) $end
|
||
|
|
$var wire 64 u1 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 q# >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(60) $end
|
||
|
|
$var wire 64 9; >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(61) $end
|
||
|
|
$var wire 64 I; >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(62) $end
|
||
|
|
$var wire 64 Y; >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(63) $end
|
||
|
|
$var wire 64 i; >>@3$value [63:0] $end
|
||
|
|
$var wire 1 Sd >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(6) $end
|
||
|
|
$var wire 64 '2 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 y# >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(7) $end
|
||
|
|
$var wire 64 72 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 #$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(8) $end
|
||
|
|
$var wire 64 G2 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 +$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module /xreg(9) $end
|
||
|
|
$var wire 64 W2 >>@3$value [63:0] $end
|
||
|
|
$var wire 1 3$ >>@3$wr $end
|
||
|
|
$upscope $end
|
||
|
|
$upscope $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(0) $end
|
||
|
|
$var wire 1 g" L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(10) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(11) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(12) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(13) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(14) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(15) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(1) $end
|
||
|
|
$var wire 1 o" L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(2) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(3) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(4) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(5) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(6) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(7) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(8) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Dmem(9) $end
|
||
|
|
$var wire 1 Sd L1_wr_a4 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(0) $end
|
||
|
|
$var wire 1 I# L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(10) $end
|
||
|
|
$var wire 1 ;$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(11) $end
|
||
|
|
$var wire 1 C$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(12) $end
|
||
|
|
$var wire 1 K$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(13) $end
|
||
|
|
$var wire 1 S$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(14) $end
|
||
|
|
$var wire 1 [$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(15) $end
|
||
|
|
$var wire 1 c$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(16) $end
|
||
|
|
$var wire 1 k$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(17) $end
|
||
|
|
$var wire 1 s$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(18) $end
|
||
|
|
$var wire 1 {$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(19) $end
|
||
|
|
$var wire 1 %% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(1) $end
|
||
|
|
$var wire 1 Q# L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(20) $end
|
||
|
|
$var wire 1 -% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(21) $end
|
||
|
|
$var wire 1 5% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(22) $end
|
||
|
|
$var wire 1 =% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(23) $end
|
||
|
|
$var wire 1 E% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(24) $end
|
||
|
|
$var wire 1 M% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(25) $end
|
||
|
|
$var wire 1 U% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(26) $end
|
||
|
|
$var wire 1 ]% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(27) $end
|
||
|
|
$var wire 1 e% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(28) $end
|
||
|
|
$var wire 1 m% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(29) $end
|
||
|
|
$var wire 1 u% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(2) $end
|
||
|
|
$var wire 1 Y# L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(30) $end
|
||
|
|
$var wire 1 }% L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(31) $end
|
||
|
|
$var wire 1 '& L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(32) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(33) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(34) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(35) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(36) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(37) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(38) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(39) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(3) $end
|
||
|
|
$var wire 1 a# L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(40) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(41) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(42) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(43) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(44) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(45) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(46) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(47) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(48) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(49) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(4) $end
|
||
|
|
$var wire 1 i# L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(50) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(51) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(52) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(53) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(54) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(55) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(56) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(57) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(58) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(59) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(5) $end
|
||
|
|
$var wire 1 q# L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(60) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(61) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(62) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(63) $end
|
||
|
|
$var wire 1 Sd L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(6) $end
|
||
|
|
$var wire 1 y# L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(7) $end
|
||
|
|
$var wire 1 #$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(8) $end
|
||
|
|
$var wire 1 +$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module L1_CPU_Xreg(9) $end
|
||
|
|
$var wire 1 3$ L1_wr_a3 $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module gen_clkP_CPU_dmem_rd_en_a5 $end
|
||
|
|
$var wire 1 gB clk_en $end
|
||
|
|
$var wire 1 +d free_clk $end
|
||
|
|
$var wire 1 Kd func_en $end
|
||
|
|
$var wire 1 y; gated_clk $end
|
||
|
|
$var wire 1 Sd gating_override $end
|
||
|
|
$var wire 1 C< latched_clk_en $end
|
||
|
|
$var wire 1 gB pwr_en $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module gen_clkP_CPU_rd_valid_a2 $end
|
||
|
|
$var wire 1 C@ clk_en $end
|
||
|
|
$var wire 1 +d free_clk $end
|
||
|
|
$var wire 1 Kd func_en $end
|
||
|
|
$var wire 1 #< gated_clk $end
|
||
|
|
$var wire 1 Sd gating_override $end
|
||
|
|
$var wire 1 K< latched_clk_en $end
|
||
|
|
$var wire 1 C@ pwr_en $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module gen_clkP_CPU_rd_valid_a3 $end
|
||
|
|
$var wire 1 QG clk_en $end
|
||
|
|
$var wire 1 +d free_clk $end
|
||
|
|
$var wire 1 Kd func_en $end
|
||
|
|
$var wire 1 +< gated_clk $end
|
||
|
|
$var wire 1 Sd gating_override $end
|
||
|
|
$var wire 1 S< latched_clk_en $end
|
||
|
|
$var wire 1 QG pwr_en $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module gen_clkP_CPU_rd_valid_a4 $end
|
||
|
|
$var wire 1 YG clk_en $end
|
||
|
|
$var wire 1 +d free_clk $end
|
||
|
|
$var wire 1 Kd func_en $end
|
||
|
|
$var wire 1 3< gated_clk $end
|
||
|
|
$var wire 1 Sd gating_override $end
|
||
|
|
$var wire 1 [< latched_clk_en $end
|
||
|
|
$var wire 1 YG pwr_en $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module gen_clkP_CPU_rd_valid_a5 $end
|
||
|
|
$var wire 1 aG clk_en $end
|
||
|
|
$var wire 1 +d free_clk $end
|
||
|
|
$var wire 1 Kd func_en $end
|
||
|
|
$var wire 1 ;< gated_clk $end
|
||
|
|
$var wire 1 Sd gating_override $end
|
||
|
|
$var wire 1 c< latched_clk_en $end
|
||
|
|
$var wire 1 aG pwr_en $end
|
||
|
|
$upscope $end
|
||
|
|
$scope module pseudo_rand $end
|
||
|
|
$var wire 257 -a DEFAULT_lfsr_a1 [256:0] $end
|
||
|
|
$var wire 257 s@ DEFAULT_lfsr_a2 [256:0] $end
|
||
|
|
$var wire 1 c@ DEFAULT_reset_a0 $end
|
||
|
|
$var wire 1 %a DEFAULT_reset_a1 $end
|
||
|
|
$var wire 257 cd LFSR_POLY [256:0] $end
|
||
|
|
$var wire 32 [d LFSR_WIDTH [31:0] $end
|
||
|
|
$var wire 257 Me SEED [256:0] $end
|
||
|
|
$var wire 32 [d WIDTH [31:0] $end
|
||
|
|
$var wire 1 +d clk $end
|
||
|
|
$var wire 257 s@ rand_vect [256:0] $end
|
||
|
|
$var wire 1 c@ reset $end
|
||
|
|
$upscope $end
|
||
|
|
$upscope $end
|
||
|
|
$upscope $end
|
||
|
|
$upscope $end
|
||
|
|
$enddefinitions $end
|
||
|
|
|
||
|
|
|
||
|
|
#0
|
||
|
|
b01111101110000000000001000010100 #
|
||
|
|
b00111001100000000000000000001010 $
|
||
|
|
b01111101101000000000001000010100 %
|
||
|
|
b01111101110011110111001000010100 &
|
||
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|
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|
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|
|
b01011010000111000100111101010101000011000101100110100001001110000100110010010111001101100001001000010010001111001100000100100010110100011001110110100001110100011001010100000011000100010111111000011001000000010011100100011010000101100010101110111100100011000 -a
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||
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b0101 Gb
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||
|
|
1+d
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||
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1;d
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