FastWaveBackend/test-vcd-files/model-sim/clkdiv2n_tb.vcd

$date
	Sat Dec 26 15:33:14 2020
$end
$version
	ModelSim Version 10.5b
$end
$timescale
	1ns
$end

$scope module clkdiv2n_tb $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$var wire 1 # clk_out $end

$scope module t1 $end
$var parameter 32 $ WIDTH $end
$var parameter 32 % N $end
$var wire 1 & clk $end
$var wire 1 ' reset $end
$var wire 1 # clk_out $end
$var reg 3 ( r_reg [2:0] $end
$var wire 1 ) r_nxt [2] $end
$var wire 1 * r_nxt [1] $end
$var wire 1 + r_nxt [0] $end
$var reg 1 , clk_track $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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#30
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#40
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#50
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#80
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#90
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#120
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#130
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#150
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#170
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#200
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#210
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#230
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#240
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#250
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#270
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#280
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#290
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#300
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#310
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#320
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#330
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#350
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#360
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#370
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#380
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#390
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#400
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#410
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b10 (
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#420
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#430
1!
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b11 (
0+
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#440
0!
0&
#450
1!
1&
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#470
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#480
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#490
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b0 (
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