92 lines
2.3 KiB
Plaintext
92 lines
2.3 KiB
Plaintext
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$date
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Thu Dec 17 17:19:03 2020
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$end
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$version
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Aldec HDL Simulator Version 10.03.3558
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$end
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$timescale
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1 ps
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$end
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$scope module tb $end
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$scope module t $end
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$var wire 1 ! CLK $end
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$var wire 1 " LED $end
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$var wire 1 # PIN_10 $end
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$var wire 1 $ PIN_11 $end
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$var wire 1 % PIN_12 $end
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$var wire 1 & PIN_13 $end
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$var wire 1 ' SPI_In $end
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$var wire 1 ( SPI_Out $end
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$var wire 1 ) SPI_Data_Available $end
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$var wire 1 * RegMap_In $end
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$var wire 1 + RegMap_Out $end
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$var wire 1 , RegMap_Data_Available $end
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$var wire 8 - AddrBus [7:0] $end
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$var wire 8 . DataBus [7:0] $end
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$scope module controller $end
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$var wire 1 ! clk $end
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$var wire 1 " LED $end
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$var wire 8 . DataBus [7:0] $end
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$var wire 1 ) SPI_Data_Available $end
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$var wire 1 , RegMap_Data_available $end
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$var wire 8 / addr [7:0] $end
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$var wire 8 0 data [7:0] $end
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$var wire 1 1 BusActive $end
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$var reg 8 2 AddrBus [7:0] $end
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$var reg 1 3 SPI_In $end
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$var reg 1 4 SPI_Out $end
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$var reg 1 5 RegMap_In $end
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$var reg 1 6 RegMap_Out $end
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$var reg 1 7 LED_state $end
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$var reg 3 8 block [2:0] $end
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$var reg 3 9 doing [2:0] $end
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$var parameter 3 : IDLE $end
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$var parameter 3 ; READ_ADDR $end
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$var parameter 3 < READ_DATA $end
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$var parameter 3 = TX $end
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$var parameter 3 > SPI $end
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$upscope $end
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$scope module reg_mag_i $end
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$var wire 1 ! clk $end
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$var wire 1 + RegMap_Out $end
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$var wire 1 * RegMap_In $end
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$var wire 8 - AddrBus [7:0] $end
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$var wire 8 . DataBus [7:0] $end
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$var wire 1 ? r_w $end
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$var wire 1 @ outputData $end
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$var wire 1 A inputData $end
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$var reg 1 B RegMap_Data_Available $end
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$var reg 8 C inData [7:0] $end
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$var reg 8 D inAddr [7:0] $end
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$var reg 8 E outData [7:0] $end
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$var reg 1 F addr_rcv $end
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$var reg 1 G data_rcv $end
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$var reg 2 H state [1:0] $end
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$var parameter 2 I INIT $end
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$var parameter 2 J IDLE $end
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$var parameter 2 K RX $end
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$var parameter 2 L TX $end
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$var parameter 32 M MAXADDRESS $end
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$upscope $end
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$scope module SPI_i $end
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$var wire 1 ! clk $end
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$var wire 1 # SCK $end
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$var wire 1 $ SSEL $end
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$var wire 1 % MOSI $end
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$var wire 1 & MISO $end
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$var wire 1 ' SPI_In $end
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$var wire 1 ( SPI_Out $end
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$var wire 8 - AddrBus [7:0] $end
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$var wire 8 . DataBus [7:0] $end
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$var wire 1 N SCK_risingedge $end
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$var wire 1 O SCK_fallingedge $end
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$var wire 1 P SSEL_active $end
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$var wire 1 Q MOSI_data $end
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$var reg 1 R SPI_Data_Available $end
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