2022-05-21 21:55:27 +00:00
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# Disclaimer
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PROPRIETARY - Copyright - Yehowshua Immanuel
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2022-04-14 04:50:37 +00:00
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# The Beginnings of a high-performance, low memory footprint VCD Viewer in Rust for massive multi-GB waveforms
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2022-05-22 00:40:46 +00:00
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## Current Features
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2022-04-14 04:50:37 +00:00
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- very fast
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2022-05-22 00:40:46 +00:00
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- loads 400MB of VCD waveform per second on an 8 core 2017 desktop CPU with NVMe storage
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2022-04-14 04:50:37 +00:00
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- consumes roughly between 10 - 50MB of memory per GB of waveform
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2022-05-22 00:40:46 +00:00
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## Planed Features
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2022-04-14 04:50:37 +00:00
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- elegant/pretty UI
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- can be easily ported to work in browser via webassembly
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- allows high-performance custom Rust plugins to manipulate and
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generate new waveforms live
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## Running
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Make sure you have a test vcd file to get you started. You can grab
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a large VCD file from
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[here](https://drive.google.com/file/d/1pfm2qo2l8fGTHHJ8TLrg1vSGaV_TUbp2/view?usp=sharing).
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The first build of the program may take some time.
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2022-05-19 00:47:55 +00:00
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``cargo run --release test-vcd-files/aldec/SPI_Write.vcd``
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2022-04-14 04:50:37 +00:00
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2022-05-19 02:57:42 +00:00
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# TODO
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- [x] We need a way to merge lines.
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2022-05-24 03:59:57 +00:00
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- [ ] Consider what to do with don't care values
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will probably just convert them to strings for now.
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- [ ] Test for speed and see if stream of bytes is helpful
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2022-05-23 03:00:03 +00:00
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- [ ] Include line and possible column numbers
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2022-05-21 02:52:26 +00:00
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- [ ] Change states to lowercase
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2022-05-19 02:57:42 +00:00
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- [ ] We need to start regression testing the parser over all files
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- [ ] Take a look at GTKWave parser to compare effificiency.
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- [ ] Send survey to community channel.
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2022-05-24 03:59:57 +00:00
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# Probably No Longer Needed
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- [ ] Should insert nodes in BFS order
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2022-05-19 07:44:24 +00:00
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# Files
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2022-05-21 19:23:33 +00:00
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- ./test-vcd-files/aldec/SPI_Write.vcd
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- ./test-vcd-files/ghdl/alu.vcd
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- ./test-vcd-files/ghdl/idea.vcd
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- ./test-vcd-files/ghdl/pcpu.vcd
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- ./test-vcd-files/gtkwave-analyzer/perm_current.vcd
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- ./test-vcd-files/icarus/CPU.vcd
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- ./test-vcd-files/icarus/rv32_soc_TB.vcd
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- ./test-vcd-files/icarus/test1.vcd
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- ./test-vcd-files/model-sim/CPU_Design.msim.vcd
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- ./test-vcd-files/model-sim/clkdiv2n_tb.vcd
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- ./test-vcd-files/my-hdl/Simple_Memory.vcd
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- ./test-vcd-files/my-hdl/sigmoid_tb.vcd
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- ./test-vcd-files/my-hdl/top.vcd
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- ./test-vcd-files/ncsim/ffdiv_32bit_tb.vcd
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- ./test-vcd-files/quartus/mipsHardware.vcd
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- ./test-vcd-files/quartus/wave_registradores.vcd
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- ./test-vcd-files/questa-sim/dump.vcd
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- ./test-vcd-files/questa-sim/test.vcd
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- ./test-vcd-files/riviera-pro/dump.vcd
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- ./test-vcd-files/systemc/waveform.vcd
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- ./test-vcd-files/treadle/GCD.vcd
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- ./test-vcd-files/vcs/Apb_slave_uvm_new.vcd
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- ./test-vcd-files/vcs/datapath_log.vcd
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- ./test-vcd-files/vcs/processor.vcd
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- ./test-vcd-files/verilator/swerv1.vcd
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- ./test-vcd-files/verilator/vlt_dump.vcd
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- ./test-vcd-files/vivado/iladata.vcd
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- ./test-vcd-files/xilinx_isim/test.vcd
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- ./test-vcd-files/xilinx_isim/test1.vcd
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- ./test-vcd-files/xilinx_isim/test2x2_regex22_string1.vcd
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