riscv-bluespec-classic/bs/Top.bs
2025-04-11 14:26:40 -04:00

91 lines
2.2 KiB
Haskell

package Top(mkTop, ITop(..)) where
import Deserializer
import Core
import Serializer
import BRAM
import CBindings
import Bus
import TagEngine
import List
import ActionSeq
import Vector
import BusTypes
import TagEngineTester
type FCLK = 25000000
type BAUD = 9600
interface ITop = {
ftdi_rxd :: Bit 1 {-# always_ready #-}
;led :: Bit 8 {-# always_ready #-}
;ftdi_txd :: Bit 1 -> Action {-# always_ready , always_enabled #-}
};
mkTop :: Module ITop
mkTop = do
fileHandle :: Handle <- openFile "compile.log" WriteMode
deserializer :: IDeserializer FCLK BAUD <- mkDeserialize fileHandle
serializer :: ISerializer FCLK BAUD <- mkSerialize fileHandle
core :: Core FCLK <- mkCore
persistLed :: Reg (Bit 8) <- mkReg 0
messageM $ "Hallo!!" + (realToString 5)
addRules $
rules
-- need new rule that always connects Bus to BusClient
"coreLedO" : when True ==>
persistLed := core.getLed
"coreCharDeviceO" : when True ==>
serializer.putBit8 core.getChar
"coreCharDeviceO" : when True ==>
serializer.putBit8 core.getChar
"coreCharDeviceI" : when True ==>
core.putChar deserializer.get
return $
interface ITop
ftdi_rxd = serializer.bitLineOut
ftdi_txd bitIn =
do
deserializer.putBitIn bitIn
led = persistLed
mkSim :: Module Empty
mkSim = do
_ :: Empty <- mkTagEngineTester
initCFunctions :: Reg Bool <- mkReg False
core :: Core FCLK <- mkCore
let busMap _ = Just 0
bus :: (Bus 4 2 2) <- mkBus busMap
addRules $
rules
"test bus": when True ==>
do
let server = (Vector.select bus.servers 0)
result <- server.consumeRequest
$display "Top.bs:74" (fshow result)
"initCFunctionsOnce": when not initCFunctions ==>
do
initTerminal
setupSigintHandler
initCFunctions := True
"coreCharDeviceO": when True ==>
do
writeCharToTerminal core.getChar
"coreCharDeviceI": when (isCharAvailable == 1) ==>
do
core.putChar getCharFromTerminal
"endSim": when wasCtrlCReceived ==>
do
restoreTerminal
$display "GOT CTRL+C"
$finish