riscv-bluespec-classic/.gitignore
2024-03-20 02:49:08 -04:00

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*.vcd
*.so
# bluespec files
*.bo
*.ba
# files generated from building/simulating core
compile.log
build_v
build_b_sim
mkSim_b_sim
verilog_RTL
# generated experiment outputs
experiments/bram/*.cxx
experiments/bram/*.h
experiments/bram/simBRAM
*.o
.vscode