package Uart(
    mkUartPhy,
    UartPhy(..)
    ) where

import Serializer
import Deserializer
import BusTypes
import Util

-- Out is out from the FPGA and In is in to the FPGA
interface (UartPhy :: # -> # -> *) clkFreq baudRate =
    bitOut :: Bit 1
    bitIn  :: Bit 1 -> Action

mkUartPhy :: (BusTypes.BusServer inFlightTransactions numClients) 
          -> Module (UartPhy clkFreq baudRate)
mkUartPhy dedicatedServerInterface = do
    fileHandle   :: Handle <- openFile "mkUartPhy.log" WriteMode
    deserializer :: Deserializer clkFreq baudRate <- mkDeserialize fileHandle
    serializer   :: Serializer clkFreq baudRate <- mkSerialize fileHandle
    return |>
        interface UartPhy
            bitOut = 1
            bitIn bitVal = do
                deserializer.putBitIn bitVal