ReferenceProjects/riscv-bluespec-classic
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Add flake #7

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Yehowshua merged 6 commits from :addflake into main 2025-04-18 19:35:19 +00:00
Conversation 1 Commits 6 Files changed 12 +5 -2
3 changed files with 5 additions and 2 deletions
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2
.gitignore vendored
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@ -16,6 +16,8 @@ verilog_RTL
# files generated for FPGA ULX3s implementation
ulx3s_fpga/mkTop.d
ulx3s_fpga/mkTop.json
ulx3s_fpga/mkTop.bit
ulx3s_fpga/mkTop.config
# generated experiment outputs
experiments/bram/*.cxx

2
Makefile
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@ -159,7 +159,7 @@ v_sim_vcd:
# ----------------------------------------------------------------
fpga:
make -C ulx3s_fpga
make -C ulx3s_fpga mkTop.bit
.PHONY: clean
clean:

3
ulx3s_fpga/makefile
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@ -5,7 +5,7 @@ IDCODE ?= 0x41113043 # 85f
all: prog
../verilog_RTL/$(TOPMODULE).v: ../src/Top.bsv
../verilog_RTL/$(TOPMODULE).v: ../bs/Top.bs
V_SIM=verilator TOPMODULE=$(TOPMODULE) make -C ../ v_compile
$(TOPMODULE).json: ../verilog_RTL/$(TOPMODULE).v
@ -21,6 +21,7 @@ $(TOPMODULE).config: $(TOPMODULE).json
--textcfg $@ \
--lpf ulx3s_v20.lpf \
--85k \
--lpf-allow-unconstrained \
--package CABGA381
$(TOPMODULE).bit: $(TOPMODULE).config