Make make fpga work

`ERROR: IO 'ftdi_txd_1' is unconstrained in LPF (override this error with --lpf-allow-unconstrained)`

.gitignore

@@ -15,6 +15,8 @@ verilog_RTL
 # files generated for FPGA ULX3s implementation
 ulx3s_fpga/mkTop.d
 ulx3s_fpga/mkTop.json
+ulx3s_fpga/mkTop.bit
+ulx3s_fpga/mkTop.config
 
 # generated experiment outputs
 experiments/bram/*.cxx

Makefile

@@ -160,7 +160,7 @@ v_sim_vcd:
 # ----------------------------------------------------------------
 
 fpga:
-	make -C ulx3s_fpga
+	make -C ulx3s_fpga mkTop.bit
 
 .PHONY: clean
 clean:

bs/Serializer.bs

@@ -49,4 +49,3 @@ mkSerialize fileHandle = do
           ftdiState := ftdiState' ftdiState
         when (ftdiState == IDLE)
       bitLineOut = ftdiTxOut
-    

flake.lock

@@ -0,0 +1,61 @@
+{
+  "nodes": {
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1735821806,
+        "narHash": "sha256-cuNapx/uQeCgeuhUhdck3JKbgpsml259sjUQnWM7zW8=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "d6973081434f88088e5321f83ebafe9a1167c367",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixpkgs-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "nixpkgs": "nixpkgs",
+        "utils": "utils"
+      }
+    },
+    "systems": {
+      "locked": {
+        "lastModified": 1681028828,
+        "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
+        "owner": "nix-systems",
+        "repo": "default",
+        "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-systems",
+        "repo": "default",
+        "type": "github"
+      }
+    },
+    "utils": {
+      "inputs": {
+        "systems": "systems"
+      },
+      "locked": {
+        "lastModified": 1731533236,
+        "narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "11707dc2f618dd54ca8739b309ec4fc024de578b",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}

flake.nix

@@ -0,0 +1,69 @@
+{
+  inputs = {
+    nixpkgs = {
+      url = "github:NixOS/nixpkgs/nixpkgs-unstable";
+    };
+    utils.url = "github:numtide/flake-utils";
+  };
+
+  outputs =
+    inputs:
+    inputs.utils.lib.eachDefaultSystem (
+      system:
+      let
+        pkgs = import inputs.nixpkgs {
+          localSystem = system;
+          overlays = [
+            (final: prev: {
+
+              riscv-bluespec-classic = pkgs.callPackage (
+                {
+                  stdenv,
+                  bluespec,
+                  nextpnr,
+                  openfpgaloader,
+                  trellis,
+                  which,
+                  yosys,
+                  TOPMODULE ? "mkTop",
+                  makeFlags ? [ ],
+                }:
+                stdenv.mkDerivation {
+                  pname = "riscv-bluespec-classic";
+                  version = "0.1.0";
+                  src = ./.;
+
+                  # Versions can be checked with
+                  # `nix eval --json ".#bluespec-joh-template.nativeBuildInputs" | nix-shell -p jq --run jq`
+                  nativeBuildInputs = [
+                    bluespec
+                    nextpnr
+                    openfpgaloader
+                    trellis
+                    which
+                    yosys
+                  ];
+
+                  # TODO: Build and install something
+
+                }
+              ) { };
+
+            })
+          ];
+        };
+      in
+      {
+        packages = {
+          default = inputs.self.packages."${system}".riscv-bluespec-classic;
+          riscv-bluespec-classic = pkgs.riscv-bluespec-classic;
+        };
+
+        devShells.default =
+          with pkgs;
+          mkShell {
+            inputsFrom = [ riscv-bluespec-classic ];
+          };
+      }
+    );
+}

shell.nix

@@ -1,14 +0,0 @@
-{ pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/d34a98666913267786d9ab4aa803a1fc75f81f4d.tar.gz") {} }:
-
-pkgs.mkShell {
-  buildInputs = [
-    pkgs.yosys
-    pkgs.nextpnr
-    pkgs.bluespec
-    pkgs.yosys-bluespec
-  ];
-
-  shellHook = ''
-    echo "Dev environment for Manna Chip."
-  '';
-}

ulx3s_fpga/makefile

@@ -5,7 +5,7 @@ IDCODE ?= 0x41113043 # 85f
 
 all: prog
 
-../verilog_RTL/$(TOPMODULE).v: ../src/Top.bsv
+../verilog_RTL/$(TOPMODULE).v: ../bs/Top.bs
 	V_SIM=verilator TOPMODULE=$(TOPMODULE) make -C ../ v_compile
 
 $(TOPMODULE).json: ../verilog_RTL/$(TOPMODULE).v
@@ -21,6 +21,7 @@ $(TOPMODULE).config: $(TOPMODULE).json
 		--textcfg $@ \
 		--lpf ulx3s_v20.lpf \
 		--85k \
+		--lpf-allow-unconstrained \
 		--package CABGA381
 
 $(TOPMODULE).bit: $(TOPMODULE).config