flake: Fix bluespec bsc binary

Nixpkgs pr incoming

.gitignore

@@ -15,6 +15,8 @@ verilog_RTL
 # files generated for FPGA ULX3s implementation
 ulx3s_fpga/mkTop.d
 ulx3s_fpga/mkTop.json
+ulx3s_fpga/mkTop.bit
+ulx3s_fpga/mkTop.config
 
 # generated experiment outputs
 experiments/bram/*.cxx

Makefile

@@ -100,7 +100,7 @@ b_all: b_compile  b_link    b_sim
 b_compile:
 	mkdir  -p build_b_sim
 	@echo Compiling for Bluesim ...
-	bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE) 
+	bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE)
 	@echo Compiling for Bluesim finished
 
 .PHONY: b_link
@@ -142,7 +142,7 @@ v_compile:
 .PHONY: v_link
 v_link: $(BDPI_OBJ)
 	@echo Linking for Verilog sim ...
-	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v 
+	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v
 	@echo Linking for Verilog sim finished
 
 .PHONY: v_sim
@@ -160,7 +160,7 @@ v_sim_vcd:
 # ----------------------------------------------------------------
 
 fpga:
-	make -C ulx3s_fpga
+	make -C ulx3s_fpga mkTop.bit
 
 .PHONY: clean
 clean:

bs/ClkDivider.bs

@@ -9,7 +9,7 @@ interface (ClkDivider :: # -> *) hi =
 
 mkClkDivider :: Handle -> Module (ClkDivider hi)
 mkClkDivider fileHandle = do
-    counter <- mkReg(0 :: UInt (TLog hi))   
+    counter <- mkReg(0 :: UInt (TLog hi))
     let hi_value :: UInt (TLog hi) = (fromInteger $ valueOf hi)
     let half_hi_value :: UInt (TLog hi) = (fromInteger $ valueOf (TDiv hi 2))
 
@@ -28,7 +28,7 @@ mkClkDivider fileHandle = do
           counter := if (counter == hi_value)
                     then 0
                     else counter + 1
-    
+
     return $
       interface ClkDivider
         reset :: Action

bs/Deserializer.bs

@@ -1,15 +1,15 @@
 package Deserializer(
   mkDeserialize,
   IDeserializer(..),
-  State(..)) 
+  State(..))
   where
 
 import ClkDivider
 import State
 
 
-interface (IDeserializer :: # -> # -> *) clkFreq baudRate = 
+interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
-  get         ::  Bit 8            
+  get         ::  Bit 8
   putBitIn    :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
 
 mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
@@ -35,10 +35,10 @@ mkDeserialize fileHandle = do
           ftdiState := ftdiState' ftdiState
 
       {-# ASSERT fire when enabled #-}
-        "SAMPLING" : when 
+        "SAMPLING" : when
           DATA(n) <- ftdiState,
           n >= 0,
-          n <= 7, 
+          n <= 7,
           let sampleTrigger = clkDivider.isHalfCycle
             in sampleTrigger
           ==>
@@ -48,6 +48,6 @@ mkDeserialize fileHandle = do
   return $
     interface IDeserializer
     {get      = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
-    ;putBitIn bit = 
+    ;putBitIn bit =
       ftdiRxIn := bit
     }

bs/Serializer.bs

@@ -1,7 +1,7 @@
 package Serializer(
   mkSerialize,
   ISerializer(..),
-  State(..)) 
+  State(..))
   where
 
 import ClkDivider
@@ -14,7 +14,7 @@ serialize ftdiState dataReg =
         (DATA n) -> dataReg[n:n]
         _        -> 1'b1
 
-interface (ISerializer :: # -> # -> *) clkFreq baudRate = 
+interface (ISerializer :: # -> # -> *) clkFreq baudRate =
   putBit8    :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
   bitLineOut ::  Bit 1            {-# always_ready #-}
 
@@ -29,8 +29,8 @@ mkSerialize fileHandle = do
   addRules $
     rules
       {-# ASSERT fire when enabled #-}
-      "ADVANCE UART STATE WHEN NOT IDLE" : when 
+      "ADVANCE UART STATE WHEN NOT IDLE" : when
-        (ftdiState /= IDLE), 
+        (ftdiState /= IDLE),
         (clkDivider.isAdvancing) ==>
         do
           ftdiState := ftdiState' ftdiState
@@ -42,11 +42,10 @@ mkSerialize fileHandle = do
 
   return $
     interface ISerializer
-      putBit8  bit8Val = 
+      putBit8  bit8Val =
         do
           clkDivider.reset
-          dataReg := bit8Val 
+          dataReg := bit8Val
           ftdiState := ftdiState' ftdiState
         when (ftdiState == IDLE)
       bitLineOut = ftdiTxOut
-    

bs/State.bs

@@ -2,15 +2,15 @@ package State(
   State(..),
   ftdiState') where
 
-data State = IDLE 
+data State = IDLE
-           | START 
+           | START
-           | DATA (UInt (TLog 8)) 
+           | DATA (UInt (TLog 8))
-           | PARITY 
+           | PARITY
            | STOP
            deriving (Bits, Eq, FShow)
 
 ftdiState' :: State -> State
-ftdiState' state = 
+ftdiState' state =
   case state of
     IDLE    -> START
     START   -> DATA(0)

flake.lock

@@ -0,0 +1,61 @@
+{
+  "nodes": {
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1743689281,
+        "narHash": "sha256-y7Hg5lwWhEOgflEHRfzSH96BOt26LaYfrYWzZ+VoVdg=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "2bfc080955153be0be56724be6fa5477b4eefabb",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixpkgs-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "nixpkgs": "nixpkgs",
+        "utils": "utils"
+      }
+    },
+    "systems": {
+      "locked": {
+        "lastModified": 1681028828,
+        "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
+        "owner": "nix-systems",
+        "repo": "default",
+        "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-systems",
+        "repo": "default",
+        "type": "github"
+      }
+    },
+    "utils": {
+      "inputs": {
+        "systems": "systems"
+      },
+      "locked": {
+        "lastModified": 1731533236,
+        "narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "11707dc2f618dd54ca8739b309ec4fc024de578b",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}

flake.nix

@@ -0,0 +1,98 @@
+{
+  inputs = {
+    nixpkgs = {
+      url = "github:NixOS/nixpkgs/nixpkgs-unstable";
+    };
+    utils.url = "github:numtide/flake-utils";
+  };
+
+  outputs =
+    inputs:
+    inputs.utils.lib.eachDefaultSystem (
+      system:
+      let
+        pkgs = import inputs.nixpkgs {
+          localSystem = system;
+          overlays = [
+            (final: prev: {
+
+              riscv-bluespec-classic = pkgs.callPackage (
+                {
+                  stdenv,
+                  bluespec,
+                  nextpnr,
+                  openfpgaloader,
+                  trellis,
+                  which,
+                  yosys,
+                }:
+                stdenv.mkDerivation {
+                  pname = "riscv-bluespec-classic";
+                  version = "0.1.0";
+                  src = ./.;
+
+                  # Versions can be checked with
+                  # `nix eval --json ".#riscv-bluespec-classic.nativeBuildInputs" | nix-shell -p jq --run jq`
+                  nativeBuildInputs = [
+                    (
+                      (bluespec.override {
+                        makeWrapper = prev.makeBinaryWrapper;
+                        withDocs = false;
+                        texliveFull = null;
+                        asciidoctor = null;
+                      }).overrideAttrs
+                      {
+                        doCheck = false;
+
+                        postFixup = ''
+                          # https://github.com/B-Lang-org/bsc/blob/65e3a87a17f6b9cf38cbb7b6ad7a4473f025c098/src/comp/bsc.hs#L1839
+                          wrapProgram $out/bin/core/bsc \
+                            --prefix PATH : ${
+                              prev.lib.makeBinPath (
+                                if stdenv.hostPlatform.isDarwin then [ prev.cctools ] else [ prev.targetPackages.stdenv.cc ]
+                              )
+                            }
+                        '';
+                      }
+                    )
+                    nextpnr
+                    openfpgaloader
+                    trellis
+                    which
+                    yosys
+                  ];
+
+                  makeFlags = [
+                    "fpga"
+                  ];
+
+                  installPhase = ''
+                    runHook preInstall
+
+                    mkdir -p "$out"
+                    cp "./ulx3s_fpga/mkTop.bit" "$out/"
+
+                    runHook postInstall
+                  '';
+
+                }
+              ) { };
+
+            })
+          ];
+        };
+      in
+      {
+        packages = {
+          default = inputs.self.packages."${system}".riscv-bluespec-classic;
+          riscv-bluespec-classic = pkgs.riscv-bluespec-classic;
+        };
+
+        devShells.default =
+          with pkgs;
+          mkShell {
+            inputsFrom = [ riscv-bluespec-classic ];
+          };
+      }
+    );
+}

shell.nix

@@ -1,14 +0,0 @@
-{ pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/d34a98666913267786d9ab4aa803a1fc75f81f4d.tar.gz") {} }:
-
-pkgs.mkShell {
-  buildInputs = [
-    pkgs.yosys
-    pkgs.nextpnr
-    pkgs.bluespec
-    pkgs.yosys-bluespec
-  ];
-
-  shellHook = ''
-    echo "Dev environment for Manna Chip."
-  '';
-}

ulx3s_fpga/makefile

@@ -5,7 +5,7 @@ IDCODE ?= 0x41113043 # 85f
 
 all: prog
 
-../verilog_RTL/$(TOPMODULE).v: ../src/Top.bsv
+../verilog_RTL/$(TOPMODULE).v: ../bs/Top.bs
 	V_SIM=verilator TOPMODULE=$(TOPMODULE) make -C ../ v_compile
 
 $(TOPMODULE).json: ../verilog_RTL/$(TOPMODULE).v
@@ -21,6 +21,7 @@ $(TOPMODULE).config: $(TOPMODULE).json
 		--textcfg $@ \
 		--lpf ulx3s_v20.lpf \
 		--85k \
+		--lpf-allow-unconstrained \
 		--package CABGA381
 
 $(TOPMODULE).bit: $(TOPMODULE).config