ReferenceProjects/riscv-bluespec-classic
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Yehowshua Immanuel 2024-03-20 02:25:31 -04:00
parent 9f90b00b25
commit e44f6b083b
11 changed files with 78 additions and 4 deletions
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4
Makefile
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@ -140,9 +140,9 @@ v_compile:
@echo Compiling for Verilog finished
.PHONY: v_link
v_link:
v_link: $(BDPI_OBJ)
@echo Linking for Verilog sim ...
bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM) verilog_RTL/$(TOPMODULE).v
bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM) verilog_RTL/$(TOPMODULE).v
@echo Linking for Verilog sim finished
.PHONY: v_sim