From d48621521aa6b6e376016ad3c4f23aa84c82404c Mon Sep 17 00:00:00 2001
From: Artturin <Artturin@artturin.com>
Date: Wed, 2 Apr 2025 03:04:44 +0300
Subject: [PATCH] Remove all trailing spaces

`git grep -I --name-only -z -e '' | xargs -0 sed -i 's/[ \t]\+\(\r\?\)$/\1/'`

Remember to setup your editor so that these are automatically removed :)
---
 Makefile           |  4 ++--
 bs/ClkDivider.bs   |  4 ++--
 bs/Deserializer.bs | 12 ++++++------
 bs/Serializer.bs   | 13 ++++++-------
 bs/State.bs        | 10 +++++-----
 5 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/Makefile b/Makefile
index 52863b1..d4d3417 100644
--- a/Makefile
+++ b/Makefile
@@ -100,7 +100,7 @@ b_all: b_compile  b_link    b_sim
 b_compile:
 	mkdir  -p build_b_sim
 	@echo Compiling for Bluesim ...
-	bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE) 
+	bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE)
 	@echo Compiling for Bluesim finished
 
 .PHONY: b_link
@@ -142,7 +142,7 @@ v_compile:
 .PHONY: v_link
 v_link: $(BDPI_OBJ)
 	@echo Linking for Verilog sim ...
-	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v 
+	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v
 	@echo Linking for Verilog sim finished
 
 .PHONY: v_sim
diff --git a/bs/ClkDivider.bs b/bs/ClkDivider.bs
index 789489e..bd016f2 100644
--- a/bs/ClkDivider.bs
+++ b/bs/ClkDivider.bs
@@ -9,7 +9,7 @@ interface (ClkDivider :: # -> *) hi =
 
 mkClkDivider :: Handle -> Module (ClkDivider hi)
 mkClkDivider fileHandle = do
-    counter <- mkReg(0 :: UInt (TLog hi))   
+    counter <- mkReg(0 :: UInt (TLog hi))
     let hi_value :: UInt (TLog hi) = (fromInteger $ valueOf hi)
     let half_hi_value :: UInt (TLog hi) = (fromInteger $ valueOf (TDiv hi 2))
 
@@ -28,7 +28,7 @@ mkClkDivider fileHandle = do
           counter := if (counter == hi_value)
                     then 0
                     else counter + 1
-    
+
     return $
       interface ClkDivider
         reset :: Action
diff --git a/bs/Deserializer.bs b/bs/Deserializer.bs
index 51c98ed..cebc355 100644
--- a/bs/Deserializer.bs
+++ b/bs/Deserializer.bs
@@ -1,15 +1,15 @@
 package Deserializer(
   mkDeserialize,
   IDeserializer(..),
-  State(..)) 
+  State(..))
   where
 
 import ClkDivider
 import State
 
 
-interface (IDeserializer :: # -> # -> *) clkFreq baudRate = 
-  get         ::  Bit 8            
+interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
+  get         ::  Bit 8
   putBitIn    :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
 
 mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
@@ -35,10 +35,10 @@ mkDeserialize fileHandle = do
           ftdiState := ftdiState' ftdiState
 
       {-# ASSERT fire when enabled #-}
-        "SAMPLING" : when 
+        "SAMPLING" : when
           DATA(n) <- ftdiState,
           n >= 0,
-          n <= 7, 
+          n <= 7,
           let sampleTrigger = clkDivider.isHalfCycle
             in sampleTrigger
           ==>
@@ -48,6 +48,6 @@ mkDeserialize fileHandle = do
   return $
     interface IDeserializer
     {get      = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
-    ;putBitIn bit = 
+    ;putBitIn bit =
       ftdiRxIn := bit
     }
\ No newline at end of file
diff --git a/bs/Serializer.bs b/bs/Serializer.bs
index acfb196..ff445fa 100644
--- a/bs/Serializer.bs
+++ b/bs/Serializer.bs
@@ -1,7 +1,7 @@
 package Serializer(
   mkSerialize,
   ISerializer(..),
-  State(..)) 
+  State(..))
   where
 
 import ClkDivider
@@ -14,7 +14,7 @@ serialize ftdiState dataReg =
         (DATA n) -> dataReg[n:n]
         _        -> 1'b1
 
-interface (ISerializer :: # -> # -> *) clkFreq baudRate = 
+interface (ISerializer :: # -> # -> *) clkFreq baudRate =
   putBit8    :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
   bitLineOut ::  Bit 1            {-# always_ready #-}
 
@@ -29,8 +29,8 @@ mkSerialize fileHandle = do
   addRules $
     rules
       {-# ASSERT fire when enabled #-}
-      "ADVANCE UART STATE WHEN NOT IDLE" : when 
-        (ftdiState /= IDLE), 
+      "ADVANCE UART STATE WHEN NOT IDLE" : when
+        (ftdiState /= IDLE),
         (clkDivider.isAdvancing) ==>
         do
           ftdiState := ftdiState' ftdiState
@@ -42,11 +42,10 @@ mkSerialize fileHandle = do
 
   return $
     interface ISerializer
-      putBit8  bit8Val = 
+      putBit8  bit8Val =
         do
           clkDivider.reset
-          dataReg := bit8Val 
+          dataReg := bit8Val
           ftdiState := ftdiState' ftdiState
         when (ftdiState == IDLE)
       bitLineOut = ftdiTxOut
-    
\ No newline at end of file
diff --git a/bs/State.bs b/bs/State.bs
index e68a482..0186f2a 100644
--- a/bs/State.bs
+++ b/bs/State.bs
@@ -2,15 +2,15 @@ package State(
   State(..),
   ftdiState') where
 
-data State = IDLE 
-           | START 
-           | DATA (UInt (TLog 8)) 
-           | PARITY 
+data State = IDLE
+           | START
+           | DATA (UInt (TLog 8))
+           | PARITY
            | STOP
            deriving (Bits, Eq, FShow)
 
 ftdiState' :: State -> State
-ftdiState' state = 
+ftdiState' state =
   case state of
     IDLE    -> START
     START   -> DATA(0)