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converted to bluespec haskell

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Yehowshua Immanuel 2024-05-19 22:16:33 -04:00
parent 72788b8436
commit cf68a5e683
17 changed files with 342 additions and 339 deletions
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.gitignore vendored
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@ -12,10 +12,14 @@ build_b_sim
mkSim_b_sim
verilog_RTL
# files generated for FPGA ULX3s implementation
ulx3s_fpga/mkTop.d
ulx3s_fpga/mkTop.json
# generated experiment outputs
experiments/bram/*.cxx
experiments/bram/*.h
experiments/bram/simBRAM
*.o
.vscode
.vscode