From 7836ac5f3fdb672efaa899848889f09ee3513db1 Mon Sep 17 00:00:00 2001 From: Artturin Date: Wed, 2 Apr 2025 03:10:29 +0300 Subject: [PATCH] Make `make fpga` work `ERROR: IO 'ftdi_txd_1' is unconstrained in LPF (override this error with --lpf-allow-unconstrained)` --- .gitignore | 2 ++ Makefile | 2 +- ulx3s_fpga/makefile | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 85c69dc..b911cdc 100644 --- a/.gitignore +++ b/.gitignore @@ -15,6 +15,8 @@ verilog_RTL # files generated for FPGA ULX3s implementation ulx3s_fpga/mkTop.d ulx3s_fpga/mkTop.json +ulx3s_fpga/mkTop.bit +ulx3s_fpga/mkTop.config # generated experiment outputs experiments/bram/*.cxx diff --git a/Makefile b/Makefile index d4d3417..1da8277 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ v_sim_vcd: # ---------------------------------------------------------------- fpga: - make -C ulx3s_fpga + make -C ulx3s_fpga mkTop.bit .PHONY: clean clean: diff --git a/ulx3s_fpga/makefile b/ulx3s_fpga/makefile index 681fade..ea44793 100644 --- a/ulx3s_fpga/makefile +++ b/ulx3s_fpga/makefile @@ -5,7 +5,7 @@ IDCODE ?= 0x41113043 # 85f all: prog -../verilog_RTL/$(TOPMODULE).v: ../src/Top.bsv +../verilog_RTL/$(TOPMODULE).v: ../bs/Top.bs V_SIM=verilator TOPMODULE=$(TOPMODULE) make -C ../ v_compile $(TOPMODULE).json: ../verilog_RTL/$(TOPMODULE).v @@ -21,6 +21,7 @@ $(TOPMODULE).config: $(TOPMODULE).json --textcfg $@ \ --lpf ulx3s_v20.lpf \ --85k \ + --lpf-allow-unconstrained \ --package CABGA381 $(TOPMODULE).bit: $(TOPMODULE).config