scaffolding for new uart interface in place

bs/Top.bs

@@ -1,8 +1,8 @@
 package Top(mkTop, ITop(..)) where
 
+import Serializer
 import Deserializer
 import Core
-import Serializer
 import BRAM
 import CBindings
 import Bus
@@ -12,6 +12,7 @@ import List
 import ActionSeq
 import Vector
 import BusTypes
+import Uart
 
 import TagEngineTester
 
@@ -27,8 +28,8 @@ interface ITop = {
 mkTop :: Module ITop
 mkTop = do
   fileHandle   :: Handle <- openFile "compile.log" WriteMode
-  deserializer :: IDeserializer FCLK BAUD <- mkDeserialize fileHandle
+  deserializer :: Deserializer FCLK BAUD <- mkDeserialize fileHandle
-  serializer   :: ISerializer FCLK BAUD <- mkSerialize fileHandle
+  serializer   :: Serializer FCLK BAUD <- mkSerialize fileHandle
   core         :: Core FCLK <- mkCore
 
   persistLed  :: Reg (Bit 8) <- mkReg 0

bs/Uart/Deserializer.bs

@@ -1,6 +1,6 @@
 package Deserializer(
   mkDeserialize,
-  IDeserializer(..),
+  Deserializer(..),
   State(..))
   where
 
@@ -8,11 +8,11 @@ import ClkDivider
 import State
 
 
-interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
+interface (Deserializer :: # -> # -> *) clkFreq baudRate =
   get         ::  Bit 8
   putBitIn    :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
 
-mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
+mkDeserialize :: Handle -> Module (Deserializer clkFreq baudRate)
 mkDeserialize fileHandle = do
   ftdiRxIn :: Wire(Bit 1) <- mkBypassWire
   shiftReg :: Reg(Bit 8) <- mkReg(0)
@@ -46,7 +46,7 @@ mkDeserialize fileHandle = do
               shiftReg := ftdiRxIn ++ shiftReg[7:1]
 
   return $
-    interface IDeserializer
+    interface Deserializer
     {get      = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
     ;putBitIn bit =
       ftdiRxIn := bit

bs/Uart/Serializer.bs

@@ -1,6 +1,6 @@
 package Serializer(
   mkSerialize,
-  ISerializer(..),
+  Serializer(..),
   State(..))
   where
 
@@ -14,11 +14,11 @@ serialize ftdiState dataReg =
         (DATA n) -> dataReg[n:n]
         _        -> 1'b1
 
-interface (ISerializer :: # -> # -> *) clkFreq baudRate =
+interface (Serializer :: # -> # -> *) clkFreq baudRate =
   putBit8    :: (Bit 8) -> Action
   bitLineOut ::  Bit 1
 
-mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
+mkSerialize :: Handle -> Module (Serializer clkFreq baudRate)
 mkSerialize fileHandle = do
 
   ftdiTxOut :: Wire(Bit 1) <- mkBypassWire
@@ -41,7 +41,7 @@ mkSerialize fileHandle = do
           ftdiTxOut := serialize ftdiState dataReg
 
   return $
-    interface ISerializer
+    interface Serializer
       putBit8  bit8Val =
         do
           clkDivider.reset

bs/Uart/Uart.bs

@@ -0,0 +1,26 @@
+package Uart(
+    mkUartPhy,
+    UartPhy(..)
+    ) where
+
+import Serializer
+import Deserializer
+import BusTypes
+import Util
+
+-- Out is out from the FPGA and In is in to the FPGA
+interface (UartPhy :: # -> # -> *) clkFreq baudRate =
+    bitOut :: Bit 1
+    bitIn  :: Bit 1 -> Action
+
+mkUartPhy :: (BusTypes.BusServer inFlightTransactions numClients) 
+          -> Module (UartPhy clkFreq baudRate)
+mkUartPhy dedicatedServerInterface = do
+    fileHandle   :: Handle <- openFile "mkUartPhy.log" WriteMode
+    deserializer :: Deserializer clkFreq baudRate <- mkDeserialize fileHandle
+    serializer   :: Serializer clkFreq baudRate <- mkSerialize fileHandle
+    return |>
+        interface UartPhy
+            bitOut = 1
+            bitIn  bitVal = do
+                action {}