need to start re-thinking structure of uart etc

2025-04-18 19:42:03 -04:00 · 2025-04-18 19:42:03 -04:00 · 44324eb803
commit 44324eb803
parent d03cceb283
5 changed files with 4 additions and 4 deletions
--- a/bs/Uart/ClkDivider.bs
+++ b/bs/Uart/ClkDivider.bs
--- a/bs/Uart/Deserializer.bs
+++ b/bs/Uart/Deserializer.bs
--- a/bs/Uart/Serializer.bs
+++ b/bs/Uart/Serializer.bs
@ -15,8 +15,8 @@ serialize ftdiState dataReg =
        _        -> 1'b1

 interface (ISerializer :: # -> # -> *) clkFreq baudRate =
-  putBit8    :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
-  bitLineOut ::  Bit 1            {-# always_ready #-}
+  putBit8    :: (Bit 8) -> Action
+  bitLineOut ::  Bit 1

 mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
 mkSerialize fileHandle = do
--- a/bs/Uart/State.bs
+++ b/bs/Uart/State.bs