ReferenceProjects/riscv-bluespec-classic
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Remove all trailing spaces

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`git grep -I --name-only -z -e '' | xargs -0 sed -i 's/[ \t]\+\(\r\?\)$/\1/'`

Remember to setup your editor so that these are automatically removed :)
This commit is contained in:
Artturin 2025-04-02 03:04:44 +03:00
parent 0dd4b60b70
commit 1622e3ab6b
6 changed files with 24 additions and 25 deletions
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4
Makefile
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@ -99,7 +99,7 @@ b_all: b_compile b_link b_sim
b_compile:
mkdir -p build_b_sim
@echo Compiling for Bluesim ...
bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE) $(TOPFILE)
bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE) $(TOPFILE)
@echo Compiling for Bluesim finished
.PHONY: b_link
@ -141,7 +141,7 @@ v_compile:
.PHONY: v_link
v_link: $(BDPI_OBJ)
@echo Linking for Verilog sim ...
bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM) verilog_RTL/$(TOPMODULE).v
bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM) verilog_RTL/$(TOPMODULE).v
@echo Linking for Verilog sim finished
.PHONY: v_sim