ReferenceProjects/fpga-starter-project-uart
2
0
Fork 0
Code Issues Pull requests 1 Actions Packages Projects Releases Wiki Activity
1 commit 3 branches 0 tags 45 KiB
Makefile 50.6%
Bluespec 49.4%
Find a file
Yehowshua Immanuel f2c06c895c first commit
2025-01-17 09:13:04 -05:00
src first commit 2025-01-17 09:13:04 -05:00
ulx3s_fpga first commit 2025-01-17 09:13:04 -05:00
.gitignore first commit 2025-01-17 09:13:04 -05:00
Makefile first commit 2025-01-17 09:13:04 -05:00
README.md first commit 2025-01-17 09:13:04 -05:00

README.md

The humble beginnings of a UART loopback.

TOPMODULE=mkTop make v_compile to generate verilog. The generated verilog can be found in the verilog_RTL/ folder.

Dependencies

You'll need to install:

  1. Yosys at git commit: 7ce5011c24b
  2. nextpnr-0.4-36-gc8406b71
  3. PrjTrellis at git commit: 1.2.1-22-g35f5aff
  4. openFPGALoader

Programming the ULX3S

Change into the folder containing this README, and then run ``

make -C ulx3s_fpga
# You may need the following line to set your screen device config
# to one parity and one stop bit. Tested working on MacOS, should
# work on Linux.
stty -f /dev/tty.usbserial-K00027 -cstopb -parenb
screen /dev/tty.usbserial-K00027 9600

Simulation

TODO

Generating Verilog

TOPMODULE=mkTop make v_compile